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target specification this is preliminary information on a new product foreseen to be developed. details are subject to change without notice. january 2012 doc id 16554 rev 3 1/120 1 stm32f103xf stm32f103xg xl-density performance line arm-b ased 32-bit mcu with 768 kb to 1 mb flash, usb, can, 17 timers, 3 adcs, 13 communication interfaces features core: arm 32-bit cortex?-m3 cpu with mpu ? 72 mhz maximum frequency, 1.25 dmips/mhz (dhrystone 2.1) performance at 0 wait state memory access ? single-cycle multiplication and hardware division memories ? 768 kbytes to 1 mbyte of flash memory ? 96 kbytes of sram ? flexible static memory controller with 4 chip select. supports compact flash, sram, psram, nor and nand memories ? lcd parallel interface, 8080/6800 modes clock, reset and supply management ? 2.0 to 3.6 v application supply and i/os ? por, pdr, and programmable voltage detector (pvd) ? 4-to-16 mhz crystal oscillator ? internal 8 mhz factory-trimmed rc ? internal 40 khz rc with calibration ? 32 khz oscillator for rtc with calibration low power ? sleep, stop and standby modes ?v bat supply for rtc and backup registers 3 12-bit, 1 s a/d converters (up to 21 channels) ? conversion range: 0 to 3.6 v ? triple-sample and hold capability ? temperature sensor 2 12-bit d/a converters dma: 12-channel dma controller ? supported peripherals: timers, adcs, dac, sdio, i 2 ss, spis, i 2 cs and usarts debug mode ? serial wire debug (swd) & jtag interfaces ? cortex-m3 embedded trace macrocell? up to 112 fast i/o ports ? 51/80/112 i/os, all mappable on 16 external interrupt vectors and almost all 5 v-tolerant up to 17 timers ? up to ten 16-bit timers, each with up to 4 ic/oc/pwm or pulse counter and quadrature (incremental) encoder input ? 2 16-bit motor control pwm timers with dead-time generation and emergency stop ? 2 watchdog timers (independent and window) ? systick timer: a 24-bit downcounter ? 2 16-bit basic timers to drive the dac up to 13 communication interfaces ? up to 2 i 2 c interfaces (smbus/pmbus) ? up to 5 usarts (iso 7816 interface, lin, irda capability, modem control) ? up to 3 spis (18 mbit/s), 2 with i 2 s interface multiplexed ? can interface (2.0b active) ? usb 2.0 full speed interface ? sdio interface crc calculation unit, 96-bit unique id ecopack ? packages table 1. device summary reference part number stm32f103xf stm32f103rf stm32f103vf stm32f103zf stm32f103xg STM32F103RG stm32f103vg stm32f103zg fbga lqfp64 10 10 mm, lqfp100 14 14 mm, lqfp144 20 20 mm lfbga144 10 10 mm www.st.com
contents stm32f103xf, stm32f103xg 2/120 doc id 16554 rev 3 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 arm ? cortex?-m3 core with embedded flash and sram . . . . . . . . . 15 2.3.2 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.3 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.4 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15 2.3.5 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.6 fsmc (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.7 lcd parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.8 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 16 2.3.9 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.10 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.11 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.12 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.13 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.14 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.15 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.16 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.17 rtc (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 19 2.3.18 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.19 i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.20 universal synchronous/asynchronous receiver transmitters (usarts) 21 2.3.21 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.22 inter-integrated sound (i 2 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.23 sdio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.24 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.25 universal serial bus (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.26 gpios (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.27 adc (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.28 dac (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
stm32f103xf, stm32f103xg contents doc id 16554 rev 3 3/120 2.3.29 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.30 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.31 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.3.2 operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 42 5.3.3 embedded reset and power control block characteristics . . . . . . . . . . . 42 5.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3.6 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3.7 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3.8 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.3.9 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.3.10 fsmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.3.12 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 82 5.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3.16 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.3.17 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.3.18 can (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . 100
contents stm32f103xf, stm32f103xg 4/120 doc id 16554 rev 3 5.3.19 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.3.20 dac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.3.21 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.2.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 115 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
stm32f103xf, stm32f103xg list of tables doc id 16554 rev 3 5/120 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f103xf and stm32f103xg features and peripheral counts . . . . . . . . . . . . . . . . . 11 table 3. stm32f103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. stm32f103xf and stm32f103xg timer feature comparison . . . . . . . . . . . . . . . . . . . . . . 19 table 5. stm32f103xf and stm32f103xg pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 6. fsmc pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 7. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 8. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 9. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 10. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 11. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 12. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 13. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 table 14. maximum current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 15. maximum current consumption in run mode, code with data processing running from ram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 16. maximum current consumption in sleep mode, code running from flash or ram. . . . . . . 46 table 17. typical and maximum current consumptions in stop and standby modes . . . . . . . . . . . . 47 table 18. typical current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 19. typical current consumption in sleep mode, code running from flash or ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 20. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 21. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 22. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 23. hse 4-16 mhz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 table 24. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 25. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 26. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 27. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 28. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 29. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 30. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 31. asynchronous non-multiplexed sram/psram/nor read timings . . . . . . . . . . . . . . . . . . 63 table 32. asynchronous non-multiplexed sram/psram/nor write timings . . . . . . . . . . . . . . . . . . 64 table 33. asynchronous read muxed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 34. asynchronous multiplexed psram/nor read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 35. asynchronous multiplexed psram/nor write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 36. synchronous multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 37. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 38. synchronous non-multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 39. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 40. switching characteristics for pc card/cf read and write cycles in attribute/common space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 41. switching characteristics for pc card/cf read and write cycles in i/o space . . . . . . . . . . 78 table 42. switching characteristics for nand flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 43. switching characteristics for nand flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
list of tables stm32f103xf, stm32f103xg 6/120 doc id 16554 rev 3 table 44. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 45. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 46. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 47. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 48. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 49. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 50. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 51. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 52. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 53. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 54. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 55. scl frequency (f pclk1 = 36 mhz.,v dd = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 56. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 57. i 2 s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 58. sd / mmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 59. usb startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 60. usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 61. usb: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 00 table 62. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 63. r ain max for f adc = 14 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 64. adc accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 table 65. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 66. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 67. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 68. lfbga144 ? 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 69. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 111 table 70. lqpf100 ? 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 112 table 71. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 113 table 72. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 73. stm32f103xf and stm32f103xg ordering information scheme . . . . . . . . . . . . . . . . . . 117
stm32f103xf, stm32f103xg list of figures doc id 16554 rev 3 7/120 list of figures figure 1. stm32f103xf and stm32f103xg performance line block diagram. . . . . . . . . . . . . . . . . 12 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. stm32f103xf and stm32f103xg xl-density performance line bga144 ballout . . . . . . 25 figure 4. stm32f103xf and stm32f103xg xl-density performance line lqfp144 pinout. . . . . . 26 figure 5. stm32f103xf and stm32f103xg xl-density performance line lqfp100 pinout. . . . . . 27 figure 6. stm32f103xf and stm32f103xg xl-density performance line lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 7. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 8. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 9. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 10. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 11. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 12. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals enabled . . . . . . . . . . . . . . . . . 45 figure 13. typical current consumption in run mode versus frequency (at 3.6 v)- code with data processing running from ram, peripherals disabled . . . . . . . . . . . . . . . . 45 figure 14. typical current consumption on v bat with rtc on vs. temperature at different v bat values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 15. typical current consumption in stop mode with regulator in run mode versus temperature at different v dd values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 16. typical current consumption in stop mode with regulator in low-power mode versus temperature at different v dd values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 17. typical current consumption in standby mode versus temperature at different v dd values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 18. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 19. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 20. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 21. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 22. asynchronous non-multiplexed sram/psram/nor read waveforms . . . . . . . . . . . . . . . 62 figure 23. asynchronous non-multiplexed sram/psram/nor write waveforms . . . . . . . . . . . . . . . 63 figure 24. asynchronous multiplexed psram/nor read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 25. asynchronous multiplexed psram/nor write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 26. synchronous multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 27. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 28. synchronous non-multiplexed nor/psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 29. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 30. pc card/compactflash controller waveforms for common memory read access . . . . . . . 73 figure 31. pc card/compactflash controller waveforms for common memory write access . . . . . . . 74 figure 32. pc card/compactflash controlle r waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 33. pc card/compactflash controlle r waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 34. pc card/compactflash controller waveforms for i/o space read access . . . . . . . . . . . . . 76 figure 35. pc card/compactflash controller waveforms for i/o space write access . . . . . . . . . . . . . 77 figure 36. nand controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 37. nand controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 38. nand controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 79 figure 39. nand controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . . 80
list of figures stm32f103xf, stm32f103xg 8/120 doc id 16554 rev 3 figure 40. standard i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 41. standard i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 figure 42. 5 v tolerant i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 43. 5 v tolerant i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 figure 44. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 45. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 46. i 2 c bus ac waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 47. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 48. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 49. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 50. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 51. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 52. sdio high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 53. sd default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 54. usb timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 55. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 56. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 57. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . 104 figure 58. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . 105 figure 59. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 60. recommended pcb design rules (0.80/0.75 mm pitch bga . . . . . . . . . . . . . . . . . . . . . . 109 figure 61. lfbga144 ? 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 62. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 63. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 64. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 112 figure 65. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 66. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 113 figure 67. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 68. lqfp100 p d max vs. t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
stm32f103xf, stm32f103xg introduction doc id 16554 rev 3 9/120 1 introduction this datasheet provides the ordering information and mechanical device characteristics of the stm32f103xf and stm32f103xg xl-density performance line microcontrollers. for more details on the whole stmicroelectronics stm32f103xx family, please refer to section 2.2: full compatibility throughout the family . the xl-density stm32f103xx datasheet should be read in conjunction with the stm32f10xxx reference manual. for information on programming, erasing and protection of the internal flash memory please refer to the stm32f10xxx flash programming manual. the reference and flash programming manuals are both available from the stmicroelectronics website www.st.com . for information on the cortex?-m3 core please refer to the cortex?-m3 technical reference manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/ .
description stm32f103xf, stm32f103xg 10/120 doc id 16554 rev 3 2 description the stm32f103xf and stm32f103xg performance line family incorporates the high- performance arm ? cortex?-m3 32-bit risc core operating at a 72 mhz frequency, high- speed embedded memories (flash memory up to 1 mbyte and sram up to 96 kbytes), and an extensive range of enhanced i/os and pe ripherals connected to two apb buses. all devices offer three 12-bit adcs, ten general-purpose 16-bit timers plus two pwm timers, as well as standard and advanced communication interfaces: up to two i 2 cs, three spis, two i 2 ss, one sdio, five usarts, an usb and a can. the stm32f103xx xl-density performance line family operates in the ?40 to +105 c temperature range, from a 2.0 to 3.6 v power supply. a comprehensive set of power-saving mode allows the design of low-power applications. these features make the stm32f103xx high-density performance line microcontroller family suitable for a wide range of applications such as motor drives, application control, medical and handheld equipment, pc and gaming peripherals, gps platforms, industrial applications, plcs, inverters, printers, scanners, alarm systems and video intercom.
stm32f103xf, stm32f103xg description doc id 16554 rev 3 11/120 2.1 device overview the stm32f103xx xl-density performance line family offers devices in four different package types: from 64 pins to 144 pins. depe nding on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. figure 1 shows the general block diagram of the device family. table 2. stm32f103xf and stm32f103xg features and peripheral counts peripherals stm32f103rx stm32f103vx stm32f103zx flash memory 768 kb 1 mb 768 kb 1 mb 768 kb 1 mb sram in kbytes 96 96 96 fsmc no yes (1) 1. for the lqfp100 package, only fsmc bank1 an d bank2 are available. bank1 can only support a multiplexed nor/psram memory using the ne1 chip select. bank2 can only support a 16- or 8-bit nand flash memory using the nce2 chip select. the interr upt line cannot be used since port g is not available in this package. ye s timers general-purpose 10 advanced-control 2 basic 2 comm spi(i 2 s) (2) 2. the spi2 and spi3 interfaces give the flexibility to wo rk in an exclusive way in either the spi mode or the i 2 s audio mode. 3(2) i 2 c2 usart 5 usb 1 can 1 sdio 1 gpios 51 80 112 12-bit adc number of channels 3 16 3 16 3 21 12-bit dac number of channels 2 2 cpu frequency 72 mhz operating voltage 2.0 to 3.6 v operating temperatures ambient temperatures: ?40 to +85 c /?40 to +105 c (see ta b l e 1 0 ) junction temperature: ?40 to + 125 c (see table 10 ) package lqfp64 lqfp 100 lqfp144, bga144
description stm32f103xf, stm32f103xg 12/120 doc id 16554 rev 3 figure 1. stm32f103xf and stm32f103xg performance line block diagram 1. t a = ?40 c to +85 c (suffix 6, see table 73 ) or ?40 c to +105 c (suffix 7, see table 73 ), junction temperature up to 105 c or 125 c, respectively. 2. af = alternate function on i/o port pin. pa[ 15:0] ext.it wwdg nvic 12 b it adc1 8 adin s common jtdi jtck/ s wclk jtm s / s wda t njtr s t jtdo =2 to 3 .6v 112 af ahb2 mo s i/ s d,mi s o, wkup f m a x : 4 8 /72 mhz v ss s cl, s da, s mba i2c2 gp dma1 xtal o s c 4-16 mhz xtal 3 2 khz a p b 1: f m a x =2 4 / 3 6mhz hclk pclk1 as af fl as h1 512 kb volt. reg. 3 . 3 vto1. 8 v power b a ck u pinterf a ce as af b us m a trix 64 b it rtc rc h s cortex-m 3 cpu i bus d bus o b l s ram 512b u s art1 u s art2 s pi2/i2 s 2 b xcan device 7ch a nnel s b a ck u p reg 4ch a nnel s tim1 4compl. s cl, s da, s mba i2c1 as af rx,tx, ct s ,rt s , u s art 3 temp s en s or 4ch,etr as af fclk rc l s s t a nd b y iwdg @v s w por / pdr s upply @vdda v bat =1. 8 vto 3 .6v ck as af rx,tx, ct s ,rt s , ck as af rx,tx, ct s ,rt s , ck as af a pb 2: f m a x =4 8 / 72 mh z nvic s pi1 mo s i,mi s o, s ck,n ss as af 12 b it adc2 if if interf a ce s upervi s ion pvd re s et int awu por tamper-rtc s y s tem s ck/ck,n ss /w s , uart4 rx,tx as af uart5 rx,tx as af re s et & clock controller pclk2 pll 12 b it dac1 if if if 12 b it dac2 dac1_out as af dac2_out as af to the 3 adc s 8 adin s common to the adc1 & 2 gp dma2 5ch a nnel s (alarm out) mclk as af mo s i/ s d,mi s o, s ck/ck,n ss /w s , mclk as af s wjtag tpiu etm tr a ce/trig traceclk traced[0: 3 ] as af u s bdm/can_rx u s bdp/can_tx s dio f s mc pclk 3 s ram 96 k b yte 64 b it 12 b it adc 3 if 5adin s on adc 3 4 4compl. bkin, etr inp u t as af pb[15:0] pc[ 15: 0] pd[15:0] pe[15:0] pf[15:0] pg[15:0] mpu 2 as af 1 as af 1 as af 4ch,etr as af 4ch,etr as af 4ch,etr as af d[7:0], cmd ck as af fl as h2 512 kb a[25:0] d[15:0] clk noe nwe ne[ 3 :0] nbl[1:0] nwait nl as af ch a nnel s ch a nnel s ch a nnel s ch a nnel s ch a nnel ch a nnel tim 8 tim9 tim10 tim11 v ref+ v ref? tim6 tim7 tim2 tim 3 tim4 tim5 tim12 tim1 3 tim14 o s c_in o s c_out o s c 3 2_in o s c 3 2_out v dd @v dd nr s t v dda v ss a v dd @v dd @v dda @v dda fl as h interf a ce fl as h interf a ce o b l 2 ch a nnel s as af 1 ch a nnel as af 1 ch a nnel as af a i17 3 52 @v dda gpio port a gpio port b gpio port c gpio port d gpio port e gpio port f gpio port g apb 3 apb2 apb1 bkin, etr inp u t as af u s b 2.0 f s device s pi 3 /i2 s3
stm32f103xf, stm32f103xg description doc id 16554 rev 3 13/120 figure 2. clock tree 1. when the hsi is used as a pll clock input, the maxi mum system clock frequency t hat can be achieved is 64 mhz. 2. for the usb function to be available, both hse and pll must be enabled, with the usbclk at 48 mhz. 3. to have an adc conversion time of 1 s, apb2 must be at 14 mhz, 28 mhz or 56 mhz. h s e o s c 4-16 mhz o s c_in o s c_out o s c 3 2_in o s c 3 2_out l s e o s c 3 2.76 8 khz h s i rc 8 mhz l s i rc 40 khz to independent w a tchdog (iwdg) pll x2, x 3 , x4 pllmul h s e = high- s peed extern a l clock s ign a l l s e = l s i = h s i = le g end: mco clock o u tp u t m a in pllxtpre /2 ..., x16 ahb pre s c a ler /1, 2..512 /2 pllclk h s i h s e apb1 pre s c a ler /1, 2, 4, 8 , 16 adc pre s c a ler /2, 4, 6, 8 adcclk pclk1 hclk pllclk to ahb bus , core, memory a nd dma u s bclk to u s b interf a ce u s b pre s c a ler /1, 1.5 to adc1, 2 or 3 l s e l s i h s i /12 8 /2 h s i h s e peripher a l s to apb1 peripher a l clock en ab le en ab le peripher a l clock apb2 pre s c a ler /1, 2, 4, 8 , 16 pclk2 tim1, 8 , 9, 10, 11 to tim1/ 8 a nd tim9/10/11 peripher a l s to apb2 peripher a l clock en ab le en ab le peripher a l clock 4 8 mhz 72 mhz m a x 72 mhz 72 mhz m a x 3 6 mhz m a x to rtc pll s rc s w mco c ss to cortex s y s tem timer / 8 clock en ab le s y s clk m a x rtcclk rtc s el[1:0] timxclk timxclk iwdgclk s y s clk fclk cortex free r u nning clock /2 tim2, 3 ,4,5,12,1 3 ,14,6,7 to tim2/ 3 /4/5/12/1 3 /14 a nd tim6/7 to s dio ahb interf a ce peripher a l clock en ab le hclk/2 to f s mc f s mcclk to s dio peripher a l clock en ab le peripher a l clock en ab le to i2 s3 to i2 s 2 peripher a l clock en ab le peripher a l clock en ab le i2 s3 clk i2 s 2clk s dioclk a i17 3 54 if (apb1 pre s c a ler =1) x1 el s e x2 if (apb2 pre s c a ler =1) x1 el s e x2 high- s peed intern a l clock s ign a l low- s peed intern a l clock s ign a l low- s peed extern a l clock s ign a l flitfclk to fl as h progr a mming interf a ce
description stm32f103xf, stm32f103xg 14/120 doc id 16554 rev 3 2.2 full compatibility throughout the family the stm32f103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. in the reference manual, the stm32f103x4 and stm32f103x6 are identified as low-density devices, the stm32f103x8 and stm32f103xb are referred to as medium-density devices, the stm32f103xc, stm32f103xd and stm32f103xe are referred to as high-density devices and the stm32f103xf and stm32f103xg are called xl-density devices. low-density, high-density and xl-density devices are an extension of the stm32f103x8/b medium-density devices, they are specified in the stm32f103x4/6, stm32f103xc/d/e and stm32f103xf/g datasheets, respectively. low-density devices feature lower flash memory and ram capacities, less timers and per ipherals. high-density devices have higher flash memory and ram capacities, and additional peripherals like sdio, fsmc, i 2 s and dac. xl-density devices bring even more flash and ram memory, and extra features, namely an mpu, a greater number of timers and a dual bank flash structure while remaining fully compatible with the other members of the family. the stm32f103x4, stm32f103x6, stm32f103xc, stm32f103xd, stm32f103xe, stm32f103xf and stm32f103xg are a drop-in replacement for the stm32f103x8/b devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. moreover, the stm32f103xx performance line fam ily is fully compatible with all existing stm32f101xx access line and stm32f102xx usb access line devices. table 3. stm32f103xx family pinout low-density devices medium-density devices high-density devices xl-density devices 16 kb flash 32 kb flash (1) 64 kb flash 128 kb flash 256 kb flash 384 kb flash 512 kb flash 768 kb flash 1 mb flash 6 kb ram 10 kb ram 20 kb ram 20 kb ram 48 or 64 kb (2) ram 64 kb ram 64 kb ram 96 kb ram 96 kb ram 144 5 usarts 4 16-bit timers, 2 basic timers 3 spis, 2 i 2 ss, 2 i2cs usb, can, 2 pwm timers 3 adcs, 2 dacs, 1 sdio fsmc (100- and 144-pin packages (3) ) 5 usarts 10 16-bit timers, 2 basic timers 3 spis, 2 i 2 ss, 2 i2cs usb, can, 2 pwm timers 3 adcs, 2 dacs, 1 sdio, cortex-m3 with mpu fsmc (100- and 144-pin packages (4) ), dual bank flash memory 100 3 usarts 3 16-bit timers 2 spis, 2 i 2 cs, usb, can, 1 pwm timer 2 adcs 64 2 usarts 2 16-bit timers 1 spi, 1 i 2 c, usb, can, 1 pwm timer 2 adcs 48 36 1. for orderable part numbers that do not show the a internal code after the temperature range code (6 or 7), the reference datasheet for electrical characteristics is that of the st m32f103x8/b medium-density devices. 2. 64 kb ram for 256 kb flash are available on devices delivered in csp packages only. 3. ports f and g are not available in devices delivered in 100-pin packages. 4. ports f and g are not available in devices delivered in 100-pin packages.
stm32f103xf, stm32f103xg description doc id 16554 rev 3 15/120 2.3 overview 2.3.1 arm ? cortex?-m3 core with embedded flash and sram the arm cortex?-m3 processor is the latest generation of arm processors for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm cortex?-m3 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. with its embedded arm core, stm32f103xf and stm32f103xg performance line family is compatible with all arm tools and software. figure 1 shows the general block diagram of the device family. 2.3.2 memory protection unit the memory protection unit (mpu) is used to separate the processing of tasks from the data protection. the mpu can manage up to 8 protection areas that can all be further divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the memory protection unit is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. it is usually managed by an rtos (real-time operating system). if a program accesses a memory location that is prohibited by the mpu, the rtos can detect it and take action. in an rtos environment, the kernel can dynamically upd ate the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it. 2.3.3 embedded flash memory 768 kbytes to 1 mbyte of embedded flash are available for storing programs and data. the flash memory is organized as two banks. t he first bank has a size of 512 kbytes. the second bank is either 256 or 512 kbytes depending on the device. this gives the device the capability of writing to one bank while executing code from the other bank (read-while-write capability). 2.3.4 crc (cyclic redundanc y check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc ca lculation unit helps co mpute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location.
description stm32f103xf, stm32f103xg 16/120 doc id 16554 rev 3 2.3.5 embedded sram 96 kbytes of embedded sram accessed (read/write) at cpu clock speed with 0 wait states. 2.3.6 fsmc (flexible static memory controller) the fsmc is embedded in the stm32f103xf and stm32f103xg performance line family. it has four chip select outputs supporting the following modes: pc card/compact flash, sram, psram, nor and nand. functionality overview: the three fsmc interrupt lines are ored in order to be connected to the nvic write fifo code execution from external memory except for nand flash and pc card the targeted frequency, f clk , is hclk/2, so external access is at 36 mhz when hclk is at 72 mhz and external access is at 24 mhz when hclk is at 48 mhz 2.3.7 lcd parallel interface the fsmc can be configured to interface seamlessly with most graphic lcd controllers. it supports the intel 8080 and motorola 6800 modes, and is flexible enough to adapt to specific lcd interfaces. this lcd parallel interface capability makes it easy to build cost- effective graphic applications using lcd modules with embedded controllers or high- performance solutions using external controllers with dedicated acceleration. 2.3.8 nested vectored interrupt controller (nvic) the stm32f103xf and stm32f103xg performance line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of cortex?-m3) and 16 priority levels. closely coupled nvic gives low latency interrupt processing interrupt entry vector table address passed directly to the core closely coupled nvic core interface allows early processing of interrupts processing of late arriving higher priority interrupts support for tail-chaining processor state automatically saved interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimal interrupt latency. 2.3.9 external interrupt /event controller (exti) the external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal apb2 cloc k period. up to 112 gp ios can be connected to the 16 external interrupt lines.
stm32f103xf, stm32f103xg description doc id 16554 rev 3 17/120 2.3.10 clocks and startup system clock selection is performed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an ex ternal 4-16 mhz clock can be selected, in which case it is monitored for failure. if failure is detected, the system automatically switches back to the internal rc oscillato r. a software interrupt is genera ted if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example with failure of an indirectly used external oscillator). several prescalers allow the configuration of the ahb frequency, the high speed apb (apb2) and the low speed apb (apb1) domains. the maximum frequency of the ahb and the high speed apb domains is 72 mhz. the maximum allowed frequency of the low speed apb domain is 36 mhz. see figure 2 for details on the clock tree. 2.3.11 boot modes at startup, boot pins are used to select one of three boot options: boot from user flash: you have an option to boot from any of two memory banks. by default, boot from flash memory bank 1 is selected. you can choose to boot from flash memory bank 2 by setting a bit in the option bytes. boot from system memory boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1. 2.3.12 power supply schemes v dd = 2.0 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through v dd pins. v ssa , v dda = 2.0 to 3.6 v: external analog power supplies for adc, dac, reset blocks, rcs and pll (minimum voltage to be applie d to vdda is 2.4 v when the adc or dac is used). v dda and v ssa must be connected to v dd and v ss , respectively. v bat = 1.8 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. for more details on how to connect power pins, refer to figure 10: power supply scheme . 2.3.13 power supply supervisor the device has an integrated power-on reset (por)/power-down reset (pdr) circuitry. it is always active, and ensures proper operation starting from/down to 2 v. the device remains in reset mode when v dd is below a specified threshold, v por/pdr , without the need for an external reset circuit. the device features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. refer to ta bl e 12: embedded reset and power control block characteristics for the values of v por/pdr and v pvd .
description stm32f103xf, stm32f103xg 18/120 doc id 16554 rev 3 2.3.14 voltage regulator the regulator has three operation modes: main (mr), low power (lpr) and power down. mr is used in the nominal regulation mode (run) lpr is used in the stop modes. power down is used in standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing ze ro consumption (but the contents of the registers and sram are lost) this regulator is always enabled after reset. it is disabled in standby mode. 2.3.15 low-power modes the stm32f103xf and stm32f103xg performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. stop mode stop mode achieves the lowest power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled. the voltage regulator can also be put either in normal or in low-power mode. the device can be woken up from stop mode by any of the exti line. the exti line source can be one of the 16 external lines, the pvd output, the rtc alarm or the usb wakeup. standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillators are also switched off. after entering standby mode, sram and register contents are lost except for registers in the backup domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin, or an rtc alarm occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode. 2.3.16 dma the flexible 12-channel general-purpose dmas (7 channels for dma1 and 5 channels for dma2) are able to manage memory-to-memory, peripheral-to-memory and memory-to- peripheral transfers. the two dma controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. each channel is connected to dedicated hardware dma requests, with support for software trigger on each channel. configuration is made by software and transfer sizes between source and destination are independent.
stm32f103xf, stm32f103xg description doc id 16554 rev 3 19/120 the dma can be used with the main peripherals: spi, i 2 c, usart, general-purpose, basic and advanced-control timers timx, dac, i 2 s, sdio and adc. 2.3.17 rtc (real-time cl ock) and backup registers the rtc and the backup registers are supplied through a switch that takes power either on v dd supply when present or through the v bat pin. the backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when v dd power is not present. they are not reset by a system or power reset, and they are not reset when the device wakes up from the standby mode. the real-time clock provides a set of continuo usly running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. it is clocke d by a 32.768 khz external crysta l, resonator or oscillator, the internal low power rc oscillator or the high -speed external clock divided by 128. the internal low-speed rc has a typical frequency of 40 khz. the rtc can be calibrated using an external 512 hz output to compensate for any natural quartz deviation. the rtc features a 32-bit programmable counter for long term measurement using the compare register to generate an alarm. a 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 khz. 2.3.18 timers and watchdogs the xl-density stm32f103xx performance line devices include up to two advanced-control timers, up to ten general-purpose timers, two basic timers, two watchdog timers and a systick timer. ta bl e 4 compares the features of the advanced-control, general-purpose and basic timers. table 4. stm32f103xf and stm32f103xg timer feature comparison timer counter resolution counter type prescaler factor dma request generation capture/compare channels complementary outputs tim1, tim8 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 ye s tim2, tim3, tim4, tim5 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 n o tim9, tim12 16-bit up any integer between 1 and 65536 no 2 no tim10, tim11 tim13, tim14 16-bit up any integer between 1 and 65536 no 1 no tim6, tim7 16-bit up any integer between 1 and 65536 ye s 0 n o
description stm32f103xf, stm32f103xg 20/120 doc id 16554 rev 3 advanced-control timers (tim1 and tim8) the two advanced-control timers (tim1 and tim8) can each be seen as a three-phase pwm multiplexed on 6 channels. they have complementary pwm outputs with programmable inserted dead-times. they can also be seen as a complete general-purpose timer. the 4 independent channels can be used for: input capture output compare pwm generation (edge or center-aligned modes) one-pulse mode output if configured as a standard 16-bit timer, it has the same features as the timx timer. if configured as the 16-bit pw m generator, it has full modu lation capability (0-100%). in debug mode, the advanced-control timer counter can be frozen and the pwm outputs disabled to turn off any power switch driven by these outputs. many features are shared with those of the general-purpose tim timers which have the same architecture. the advanced-control timer can therefore work together with the tim timers via the timer link feature for synchronization or event chaining. general-purpose timers (timx) there are10 synchronizable general-purpose timers embedded in the stm32f103xf and stm32f103xg performance line devices (see ta b l e 4 for differences). tim2, tim3, tim4, tim5 there are up to 4 synchronizable general-purpose timers (tim2, tim3, tim4 and tim5) embedded in the stm32f103xf and stm32f103xg access line devices. these timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, pwm or one-pulse mode output. this gives up to 16 input captures / output compares / pwms on the largest packages. their counter can be frozen in debug mode. any of the general-purpose timers can be used to generate pwm outputs. they all have independent dma request generation. these timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. tim10, tim11 and tim9 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim10 and tim11 feature one independent channel, whereas tim9 has two independent channels for input capture/output compare, pwm or one-pulse mode output. they can be synchronized with the tim2, tim3, tim4, tim5 full-featured general-purpose timers. they can also be used as simple time bases. tim13, tim14 and tim12 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim13 and tim14 feature one independent channel, whereas tim12 has two independent channels for input capture/output compare, pwm or one-pulse mode output. they can be synchronized with the tim2, tim3, tim4, tim5 full-featured general-purpose timers. they can also be used as simple time bases.
stm32f103xf, stm32f103xg description doc id 16554 rev 3 21/120 basic timers tim6 and tim7 these timers are mainly used for dac trigger generation. they can also be used as a generic 16-bit time base. independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. window watchdog the window watchdog is based on a 7-bit downcoun ter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrup t capability and the counter can be frozen in debug mode. systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: a 24-bit down counter autoreload capability maskable system interrupt generation when the counter reaches 0. programmable clock source 2.3.19 i2c bus up to two i2c bus interfaces can operate in multimaster and slave modes. they can support standard and fast modes. they support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). a hardware crc generation/verification is embedded. they can be served by dma and they support smbus 2.0/pmbus. 2.3.20 universal sync hronous/asynchronous receiver transmitters (usarts) the stm32f103xf and stm32f103xg performance line embeds three universal synchronous/asynchronous receiver transmitters (usart1, usart2 and usart3) and two universal asynchronous receiver transmitters (uart4 and uart5). these five interfaces provide asynchronous communication, irda sir endec support, multiprocessor communication mode, single-wire half-duplex communication mode and have lin master/slave capability. the usart1 interface is able to communicate at speeds of up to 4.5 mbit/s. the other available interfaces communicate at up to 2.25 mbit/s. usart1, usart2 and usart3 also provide hardware management of the cts and rts signals, smart card mode (iso 7816 complia nt) and spi-like communication capability. all interfaces can be served by the dma controller except for uart5.
description stm32f103xf, stm32f103xg 22/120 doc id 16554 rev 3 2.3.21 serial perip heral interface (spi) up to three spis are able to communicate up to 18 mbits/s in slave and master modes in full-duplex and simplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card/mmc modes. all spis can be served by the dma controller. 2.3.22 inter-integrated sound (i 2 s) two standard i 2 s interfaces (multiplexed with spi2 and spi3) are available, that can be operated in master or slave mode. these interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. audio sampling frequencies from 8 khz up to 48 khz are supported. when either or both of the i 2 s interfaces is/are configured in master mode, the master clock can be output to the external dac/codec at 256 times the sampling frequency. 2.3.23 sdio an sd/sdio/mmc host interface is availabl e, that supports mu ltimediacard system specification version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. the interface allows data transfer at up to 48 mhz in 8-bit mode, and is compliant with sd memory card specifications version 2.0. the sdio card specification version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. the current version supports only one sd/sdio/mmc4.2 card at any one time and a stack of mmc4.1 or previous. in addition to sd/sdio/mmc, this interface is also fully compliant with the ce-ata digital protocol rev1.1. 2.3.24 controller area network (can) the can is compliant with specifications 2.0a and b (active) with a bit rate up to 1 mbit/s. it can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. it has three transmit mailboxes, two receive fifos with 3 stages and 14 scalable filter banks. 2.3.25 universal serial bus (usb) the stm32f103xf and stm32f103xg performance line embed a usb device peripheral compatible with the usb full-speed 12 mbs. the usb interface implements a full-speed (12 mbit/s) function interface. it has software-configurable endpoint setting and suspend/resume support. the dedicated 48 mhz clock is generated from the internal main pll (the clock source must use a hse crystal oscillator). 2.3.26 gpios (genera l-purpose inputs/outputs) each of the gpio pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high current- capable.
stm32f103xf, stm32f103xg description doc id 16554 rev 3 23/120 the i/os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. 2.3.27 adc (analog to digital converter) three 12-bit analog-to-digital converters are embedded into stm32f103xf and stm32f103xg performance line devices and each adc shares up to 21 external channels, performing conversions in single-shot or scan modes. in scan mode, automatic conversion is performed on a selected group of analog inputs. additional logic functions embedded in the adc interface allow: simultaneous sample and hold interleaved sample and hold single shunt the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. the events generated by the general-purpose timers (timx) and the advanced-control timers (tim1 and tim8) can be internally connected to the adc start trigger and injection trigger, respectively, to allow the applicatio n to synchronize a/d conversion and timers. 2.3.28 dac (digital-t o-analog converter) the two 12-bit buffered dac channels can be used to convert two digital signals into two analog voltage signal outputs. the chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. this dual digital interface supports the following features: two dac converters: one for each output channel 8-bit or 12-bit monotonic output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual dac channel independent or simultaneous conversions dma capability for each channel external triggers for conversion input voltage reference v ref+ eight dac trigger inputs are used in the stm32f103xf and stm32f103xg performance line family. the dac channels are triggered through the timer update outputs that are also connected to different dma channels.
description stm32f103xf, stm32f103xg 24/120 doc id 16554 rev 3 2.3.29 temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 2 v < v dda < 3.6 v. the temperature sensor is internally connected to the adc1_in16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.30 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jtag tms and tck pins are shared respectively with swdio and swclk and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. 2.3.31 embedded trace macrocell? the arm ? embedded trace macrocell provides a greater visibilit y of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32f10xxx through a small number of etm pins to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using usb, ethernet, or any other high-speed channel. real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. tpa hardware is commercially available from common development tool vendors. it operates with third party debugger software tools.
stm32f103xf, stm32f103xg pinouts and pin descriptions doc id 16554 rev 3 25/120 3 pinouts and pin descriptions figure 3. stm32f103xf and stm32f103xg xl-density performance line bga144 ballout ai1479 8b v dd_7 pc 3 pc2 pf6 v dd_6 v ss _4 pf 8 h v dd_1 d pg1 3 pg14 pe6 pe5 c pg10 pg11 v dd_5 pb 8 nr s t b pg12 pg15 pc15- o s c 3 2_out pb9 a 8 7 6 5 4 3 2 1 v bat o s c_in o s c_out v ss _5 g f e pf7 pc0 pf0 pf1 pf2 v ss _10 pg9 pf4 pf 3 v ss _ 3 pf5 v dd_ 8 v dd_ 3 v dd_4 v ss _ 8 pe4 pb5 pb6 boot0 pb7 v ss _11 pf10 pc1 v dd_11 v dd_10 pf9 10 9 k j v ss _2 pd 3 pd4 pd1 pc12 pc11 pd5 pd2 pd0 v dd_9 v ss _9 v dd_2 pg1 pc5 pa5 pe9 pb2/ boot1 pc4 pa4 pe10 pg0 pf1 3 v ref? pe12 v ss a pa1 pe1 3 pa0-wkup pd9 pd10 pg4 pd1 3 12 11 pg 8 pa10 nc pa9 pa11 pa12 pc10 pc9 pa 8 pc7 pc6 pc 8 pd14 pg 3 pg2 pd15 m l pf15 pb1 pa7 pe7 pf12 pb0 pa6 pe 8 pf14 pf11 v dda pe14 v ref+ pa 3 pe15 pa2 pb10 pd 8 pd12 pb11 pb12 pb14 pb15 pb1 3 pc1 3 - tamper-rtc pe 3 pe2 pe1 pe0 pb4 jtr s t pb 3 jtdo pd6 pd7 pa15 jtdi pa14 jtck pa1 3 jtm s pe11 v ss _6 v ss _7 v ss _1 pg7 pd11 pg5 pg6 pc14- o s c 3 2_in
pinouts and pin descriptions stm32f103xf, stm32f103xg 26/120 doc id 16554 rev 3 figure 4. stm32f103xf and stm32f103xg xl -density performance line lqfp144 pinout v dd_3 v ss_3 pe1 pe0 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pg15 v dd_11 v ss_11 pg14 pg13 pg12 pg11 pg10 pg9 pd7 pd6 v dd_10 v ss_10 pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc11 pc10 pa15 pa14 pe2 v dd_2 pe3 v ss_2 pe4 nc pe5 pa13 pe6 pa12 vbat pa11 pc13-tamper-rtc pa10 pc14-osc32_in pa9 pc15-osc32_out pa8 pf0 pc9 pf1 pc8 pf2 pc7 pf3 pc6 pf4 v dd_9 pf5 v ss_9 v ss_5 pg8 v dd_5 pg7 pf6 pg6 pf7 pg5 pf8 pg4 pf9 pg3 pf10 pg2 osc_in pd15 osc_out pd14 nrst v dd_8 pc0 v ss_8 pc1 pd13 pc2 pd12 pc3 pd11 v ssa pd10 v ref- pd9 v ref+ pd8 v dda pb15 pa0-wkup pb14 pa1 pb13 pa2 pb12 pa3 v ss_4 v dd_4 pa4 pa5 pa6 pa7 pc4 pc5 pb0 pb1 pb2 pf11 pf12 vss_6 v dd_6 pf13 pf14 pf15 pg0 pg1 pe7 pe8 pe9 v ss_7 v dd_7 pe10 pe11 pe12 pe13 pe14 pe15 pb10 pb11 v ss_1 v dd_1 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 109 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 72 lqfp144 120 119 118 117 116 115 114 113 112 111 110 61 62 63 64 65 66 67 68 69 70 71 26 27 28 29 30 31 32 33 34 35 36 83 82 81 80 79 78 77 76 75 74 73 ai14667
stm32f103xf, stm32f103xg pinouts and pin descriptions doc id 16554 rev 3 27/120 figure 5. stm32f103xf and stm32f103xg xl-density performance line lqfp100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 vdd_2 vss_2 nc pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pc9 pc8 pc7 pc6 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pb15 pb14 pb13 pb12 pa 3 vss_4 vdd_4 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pe7 pe8 pe9 pe10 pe11 pe12 pe13 pe14 pe15 pb10 pb11 vss_1 vdd_1 vdd_3 vss_3 pe1 pe0 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc11 pc10 pa15 pa14 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 pe2 pe3 pe4 pe5 pe6 vbat pc13-tamper-rtc pc14-osc32_in pc15-osc32_out vss_5 vdd_5 osc_in osc_out nrst pc0 pc1 pc2 pc3 vssa vref- vref+ vdda pa 0 - w k u p pa 1 pa 2 ai14391 lqfp100
pinouts and pin descriptions stm32f103xf, stm32f103xg 28/120 doc id 16554 rev 3 figure 6. stm32f103xf and stm32f103xg xl-density performance line lqfp64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vbat pc13-tamper-rtc pc14-osc32_in pc15-osc32_out pd0 osc_in pd1 osc_out nrst pc0 pc1 pc2 pc3 vssa vdda pa 0 - w k u p pa 1 pa 2 vdd_3 vss_3 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd2 pc12 pc11 pc10 pa 1 5 pa 1 4 vdd_2 vss_2 pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pc9 pc8 pc7 pc6 pb15 pb14 pb13 pb12 pa 3 vss_4 vdd_4 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pb10 pb11 vss_1 vdd_1 lqfp64 ai14392
stm32f103xf, stm32f103xg pinouts and pin descriptions doc id 16554 rev 3 29/120 table 5. stm32f103xf and stm32f103xg pin definitions pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lfbga144 lqfp64 lqfp100 lqfp144 default remap a3 - 1 1 pe2 i/o ft pe2 traceck / fsmc_a23 a2 - 2 2 pe3 i/o ft pe3 traced0 / fsmc_a19 b2 - 3 3 pe4 i/o ft pe4 traced1/ fsmc_a20 b3 - 4 4 pe5 i/o ft pe5 traced2/ fsmc_a21 tim9_ch1 b4 - 5 5 pe6 i/o ft pe6 traced3 / fsmc_a22 tim9_ch2 c2 1 6 6 v bat sv bat a1 2 7 7 pc13-tamper- rtc (5) i/o pc13 (6) tamper-rtc b1 3 8 8 pc14-osc32_in (5) i/o pc14 (6) osc32_in c1 4 9 9 pc15- osc32_out (5) i/o pc15 (6) osc32_out c3 - - 10 pf0 i/o ft pf0 fsmc_a0 c4 - - 11 pf1 i/o ft pf1 fsmc_a1 d4 - - 12 pf2 i/o ft pf2 fsmc_a2 e2 - - 13 pf3 i/o ft pf3 fsmc_a3 e3 - - 14 pf4 i/o ft pf4 fsmc_a4 e4 - - 15 pf5 i/o ft pf5 fsmc_a5 d2 - 10 16 v ss_5 sv ss_5 d3 - 11 17 v dd_5 sv dd_5 f3 - - 18 pf6 i/o pf6 adc3_in4 / fsmc_niord tim10_ch1 f2 - - 19 pf7 i/o pf7 adc3_in5 / fsmc_nreg tim11_ch1 g3 - - 20 pf8 i/o pf8 adc3_in6 / fsmc_niowr tim13_ch1 g2 - - 21 pf9 i/o pf9 adc3_in7 / fsmc_cd tim14_ch1 g1 - - 22 pf10 i/o pf10 adc3_in8 / fsmc_intr d1 5 12 23 osc_in i osc_in pd0 (7) e1 6 13 24 osc_out o osc_out pd1 (7) f1 7 14 25 nrst i/o nrst h1 8 15 26 pc0 i/o pc0 adc123_in10 h2 9 16 27 pc1 i/o pc1 adc123_in11 h3 10 17 28 pc2 i/o pc2 adc123_in12 h4 11 18 29 pc3 i/o pc3 adc123_in13 j1 12 19 30 v ssa sv ssa k1 - 20 31 v ref- sv ref-
pinouts and pin descriptions stm32f103xf, stm32f103xg 30/120 doc id 16554 rev 3 l1 - 21 32 v ref+ sv ref+ m1 13 22 33 v dda sv dda j2 14 23 34 pa0-wkup i/o pa0 wkup/usart2_cts (8) / adc123_in0 / tim2_ch1_etr / tim5_ch1 / tim8_etr k2 15 24 35 pa1 i/o pa1 usart2_rts (7) / adc123_in1 / tim5_ch2 / tim2_ch2 (7) l2 16 25 36 pa2 i/o pa2 usart2_tx (7) / tim5_ch3 / adc123_in2 / tim9_ch1 / tim2_ch3 (7) m2 17 26 37 pa3 i/o pa3 usart2_rx (7) / tim5_ch4 / adc123_in3 / tim2_ch4 (7) / tim9_ch2 g4 18 27 38 v ss_4 sv ss_4 f4 19 28 39 v dd_4 sv dd_4 j3 20 29 40 pa4 i/o pa4 spi1_nss (7) / usart2_ck (7) / dac_out1 / adc12_in4 k3 21 30 41 pa5 i/o pa5 spi1_sck (7) / dac_out2 / adc12_in5 l3 22 31 42 pa6 i/o pa6 spi1_miso (7) / tim8_bkin / adc12_in6 / tim3_ch1 (7) / tim13_ch1 tim1_bkin m3 23 32 43 pa7 i/o pa7 spi1_mosi (7) / tim8_ch1n / adc12_in7 / tim3_ch2 (7) / tim14_ch1 tim1_ch1n j4 24 33 44 pc4 i/o pc4 adc12_in14 k4 25 34 45 pc5 i/o pc5 adc12_in15 l4 26 35 46 pb0 i/o pb0 adc12_in8 / tim3_ch3 / tim8_ch2n tim1_ch2n m4 27 36 47 pb1 i/o pb1 adc12_in9 / tim3_ch4 (7) / tim8_ch3n tim1_ch3n j5 28 37 48 pb2 i/o ft pb2/boot1 m5 - - 49 pf11 i/o ft pf11 fsmc_nios16 l5 - - 50 pf12 i/o ft pf12 fsmc_a6 h5 - - 51 v ss_6 sv ss_6 g5 - - 52 v dd_6 sv dd_6 k5 - - 53 pf13 i/o ft pf13 fsmc_a7 table 5. stm32f103xf and stm32f103xg pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lfbga144 lqfp64 lqfp100 lqfp144 default remap
stm32f103xf, stm32f103xg pinouts and pin descriptions doc id 16554 rev 3 31/120 m6 - - 54 pf14 i/o ft pf14 fsmc_a8 l6 - - 55 pf15 i/o ft pf15 fsmc_a9 k6 - - 56 pg0 i/o ft pg0 fsmc_a10 j6 - - 57 pg1 i/o ft pg1 fsmc_a11 m7 - 38 58 pe7 i/o ft pe7 fsmc_d4 tim1_etr l7 - 39 59 pe8 i/o ft pe8 fsmc_d5 tim1_ch1n k7 - 40 60 pe9 i/o ft pe9 fsmc_d6 tim1_ch1 h6 - - 61 v ss_7 sv ss_7 g6 - - 62 v dd_7 sv dd_7 j7 - 41 63 pe10 i/o ft pe10 fsmc_d7 tim1_ch2n h8 - 42 64 pe11 i/o ft pe11 fsmc_d8 tim1_ch2 j8 - 43 65 pe12 i/o ft pe12 fsmc_d9 tim1_ch3n k8 - 44 66 pe13 i/o ft pe13 fsmc_d10 tim1_ch3 l8 - 45 67 pe14 i/o ft pe14 fsmc_d11 tim1_ch4 m8 - 46 68 pe15 i/o ft pe15 fsmc_d12 tim1_bkin m9 29 47 69 pb10 i/o ft pb10 i2c2_scl / usart3_tx (7) tim2_ch3 m10 30 48 70 pb11 i/o ft pb11 i2c2_sda / usart3_rx (7) tim2_ch4 h7 31 49 71 v ss_1 sv ss_1 g7 32 50 72 v dd_1 sv dd_1 m11 33 51 73 pb12 i/o ft pb12 spi2_nss / i2s2_ws / i2c2_smba / usart3_ck (7) / tim1_bkin (7) m12 34 52 74 pb13 i/o ft pb13 spi2_sck / i2s2_ck / usart3_cts (7) / tim1_ch1n l11 35 53 75 pb14 i/o ft pb14 spi2_miso / tim1_ch2n / usart3_rts (7) / tim12_ch1 l12 36 54 76 pb15 i/o ft pb15 spi2_mosi / i2s2_sd / tim1_ch3n (7) / tim12_ch2 l9 - 55 77 pd8 i/o ft pd8 fsmc_d13 usart3_tx k9 - 56 78 pd9 i/o ft pd9 fsmc_d14 usart3_rx j9 - 57 79 pd10 i/o ft pd10 fsmc_d15 usart3_ck h9 - 58 80 pd11 i/o ft pd11 fsmc_a16 usart3_cts l10 - 59 81 pd12 i/o ft pd12 fsmc_a17 tim4_ch1 / usart3_rts table 5. stm32f103xf and stm32f103xg pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lfbga144 lqfp64 lqfp100 lqfp144 default remap
pinouts and pin descriptions stm32f103xf, stm32f103xg 32/120 doc id 16554 rev 3 k10 - 60 82 pd13 i/o ft pd13 fsmc_a18 tim4_ch2 g8 - - 83 v ss_8 sv ss_8 f8 - - 84 v dd_8 sv dd_8 k11 - 61 85 pd14 i/o ft pd14 fsmc_d0 tim4_ch3 k12 - 62 86 pd15 i/o ft pd15 fsmc_d1 tim4_ch4 j12 - - 87 pg2 i/o ft pg2 fsmc_a12 j11 - - 88 pg3 i/o ft pg3 fsmc_a13 j10 - - 89 pg4 i/o ft pg4 fsmc_a14 h12 - - 90 pg5 i/o ft pg5 fsmc_a15 h11 - - 91 pg6 i/o ft pg6 fsmc_int2 h10 - - 92 pg7 i/o ft pg7 fsmc_int3 g11 - - 93 pg8 i/o ft pg8 g10 - - 94 v ss_9 sv ss_9 f10 - - 95 v dd_9 sv dd_9 g12 37 63 96 pc6 i/o ft pc6 i2s2_mck / tim8_ch1 / sdio_d6 tim3_ch1 f12 38 64 97 pc7 i/o ft pc7 i2s3_mck / tim8_ch2 / sdio_d7 tim3_ch2 f11 39 65 98 pc8 i/o ft pc8 tim8_ch3 / sdio_d0 tim3_ch3 e11 40 66 99 pc9 i/o ft pc9 tim8_ch4 / sdio_d1 tim3_ch4 e 1 2 4 1 6 7 1 0 0 pa 8 i / o f t pa 8 usart1_ck / tim1_ch1 (7) / mco d 1 2 4 2 6 8 1 0 1 pa 9 i / o f t pa 9 u s a rt 1 _ t x (7) / tim1_ch2 (7) d11 43 69 102 pa10 i/o ft pa10 usart1_rx (7) / tim1_ch3 (7) c12 44 70 103 pa11 i/o ft pa11 usart1_cts / usbdm / can_rx (7) / tim1_ch4 (7) b12 45 71 104 pa12 i/o ft pa12 usart1_rts / usbdp / can_tx (7) / tim1_etr (7) a12 46 72 105 pa13 i/o ft jtms- swdio pa 1 3 c11 - 73 106 not connected g9 47 74 107 v ss_2 sv ss_2 f9 48 75 108 v dd_2 sv dd_2 a11 49 76 109 pa 1 4 i / o f t jtck- swclk pa 1 4 table 5. stm32f103xf and stm32f103xg pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lfbga144 lqfp64 lqfp100 lqfp144 default remap
stm32f103xf, stm32f103xg pinouts and pin descriptions doc id 16554 rev 3 33/120 a10 50 77 110 pa15 i/o ft jtdi spi3_nss / i2s3_ws tim2_ch1_etr pa15 / spi1_nss b11 51 78 111 pc10 i/o ft pc10 uart4_tx / sdio_d2 usart3_tx b10 52 79 112 pc11 i/o ft pc11 uart4_rx / sdio_d3 usart3_rx c10 53 80 113 pc12 i/o ft pc12 uart5_tx / sdio_ck usart3_ck e10 - 81 114 pd0 i/o ft pd0 fsmc_d2 (9) can_rx d10 - 82 115 pd1 i/o ft pd1 fsmc_d3 (9) can_tx e9 54 83 116 pd2 i/o ft pd2 tim3_etr / uart5_rx / sdio_cmd d9 - 84 117 pd3 i/o ft pd3 fsmc_clk usart2_cts c9 - 85 118 pd4 i/o ft pd4 fsmc_noe usart2_rts b9 - 86 119 pd5 i/o ft pd5 fsmc_nwe usart2_tx e7 - - 120 v ss_10 sv ss_10 f7 - - 121 v dd_10 sv dd_10 a8 - 87 122 pd6 i/o ft pd6 fsmc_nwait usart2_rx a9 - 88 123 pd7 i/o ft pd7 fsmc_ne1 / fsmc_nce2 usart2_ck e8 - - 124 pg9 i/o ft pg9 fsmc_ne2 / fsmc_nce3 d8 - - 125 pg10 i/o ft pg10 fsmc_nce4_1 / fsmc_ne3 c8 - - 126 pg11 i/o ft pg11 fsmc_nce4_2 b8 - - 127 pg12 i/o ft pg12 fsmc_ne4 d7 - - 128 pg13 i/o ft pg13 fsmc_a24 c7 - - 129 pg14 i/o ft pg14 fsmc_a25 e6 - - 130 v ss_11 s v ss_11 f6 - - 131 v dd_11 s v dd_11 b7 - - 132 pg15 i/o ft pg15 a7 55 89 133 pb3/ i/o ft jtdo spi3_sck / i2s3_ck/ pb3/traceswo tim2_ch2 / spi1_sck a6 56 90 134 pb4 i/o ft njtrst spi3_miso pb4 / tim3_ch1 spi1_miso b6 57 91 135 pb5 i/o pb5 i2c1_smba / spi3_mosi / i2s3_sd tim3_ch2 / spi1_mosi c6 58 92 136 pb6 i/o ft pb6 i2c1_scl (8) / tim4_ch1 (8) usart1_tx d6 59 93 137 pb7 i/o ft pb7 i2c1_sda (8) / fsmc_nadv / tim4_ch2 (8) usart1_rx table 5. stm32f103xf and stm32f103xg pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lfbga144 lqfp64 lqfp100 lqfp144 default remap
pinouts and pin descriptions stm32f103xf, stm32f103xg 34/120 doc id 16554 rev 3 d5 60 94 138 boot0 i boot0 c5 61 95 139 pb8 i/o ft pb8 tim4_ch3 (8) / sdio_d4 / tim10_ch1 i2c1_scl/ can_rx b5 62 96 140 pb9 i/o ft pb9 tim4_ch4 (8) / sdio_d5 / tim11_ch1 i2c1_sda / can_tx a5 - 97 141 pe0 i/o ft pe0 tim4_etr / fsmc_nbl0 a4 - 98 142 pe1 i/o ft pe1 fsmc_nbl1 e5 63 99 143 v ss_3 sv ss_3 f5 64 100 144 v dd_3 sv dd_3 1. i = input, o = output, s = supply. 2. ft = 5 v tolerant. 3. function availability depends on the chosen device. 4. if several peripherals share the same i/o pin, to avoid conflict between these alte rnate functions only one peripheral should be enabled at a time through the peri pheral clock enable bit (in the correspondi ng rcc peripheral clock enable register). 5. pc13, pc14 and pc15 are supplied through the power switch. sinc e the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 in output mode is li mited: the speed should not exceed 2 mhz with a maximum load of 30 pf and these ios must not be used as a current source (e.g. to drive an led). 6. main function after the first backup domain power-up. later on, it depends on the contents of the backup registers even after reset (because these registers are not reset by the main reset). for details on how to manage these ios, refer to the battery backup domain and bkp register description sections in the stm32f10xxx reference manual, available from the stmicroelectronics website: www.st.com. 7. for the lqfp64 package, the pins number 5 and 6 are c onfigured as osc_in/osc_out after reset, however the functionality of pd0 and pd1 can be remapped by softwa re on these pins. for the lqfp100 and lqfp144/bga144 packages, pd0 and pd1 are available by def ault, so there is no need for remapping. for more details, refer to alternate function i/o and debug configuration section in the stm32f10xxx reference manual. 8. this alternate function can be remapped by software to some other port pins (if available on the used package). for more details, refer to the alternate function i/o and debug conf iguration section in the st m32f10xxx reference manual, available from the stmicroel ectronics website: www.st.com. 9. for devices delivered in lq fp64 packages, the fsmc f unction is not available. table 5. stm32f103xf and stm32f103xg pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lfbga144 lqfp64 lqfp100 lqfp144 default remap
stm32f103xf, stm32f103xg pinouts and pin descriptions doc id 16554 rev 3 35/120 table 6. fsmc pin definition pins fsmc lqfp100 (1) cf cf/ide nor/psram/ sram nor/psram mux nand 16 bit pe2 a23 a23 yes pe3 a19 a19 yes pe4 a20 a20 yes pe5 a21 a21 yes pe6 a22 a22 yes pf0 a0 a0 a0 - pf1 a1 a1 a1 - pf2 a2 a2 a2 - pf3 a3 a3 - pf4 a4 a4 - pf5 a5 a5 - pf6 niord niord - pf7 nreg nreg - pf8 niowr niowr - pf9 cd cd - pf10 intr intr - pf11 nios16 nios16 - pf12 a6 a6 - pf13 a7 a7 - pf14 a8 a8 - pf15 a9 a9 - pg0 a10 a10 - pg1 a11 - pe7 d4 d4 d4 da4 d4 yes pe8 d5 d5 d5 da5 d5 yes pe9 d6 d6 d6 da6 d6 yes pe10 d7 d7 d7 da7 d7 yes pe11 d8 d8 d8 da8 d8 yes pe12 d9 d9 d9 da9 d9 yes pe13 d10 d10 d10 da10 d10 yes pe14 d11 d11 d11 da11 d11 yes pe15 d12 d12 d12 da12 d12 yes pd8 d13 d13 d13 da13 d13 yes
pinouts and pin descriptions stm32f103xf, stm32f103xg 36/120 doc id 16554 rev 3 pd9 d14 d14 d14 da14 d14 yes pd10 d15 d15 d15 da15 d15 yes pd11 a16 a16 cle yes pd12 a17 a17 ale yes pd13 a18 a18 yes pd14 d0 d0 d0 da0 d0 yes pd15 d1 d1 d1 da1 d1 yes pg2 a12 - pg3 a13 - pg4 a14 - pg5 a15 - pg6 int2 - pg7 int3 - pd0 d2 d2 d2 da2 d2 yes pd1 d3 d3 d3 da3 d3 yes pd3 clk clk yes pd4 noe noe noe noe noe yes pd5 nwe nwe nwe nwe nwe yes pd6 nwait nwait nwait nwait nwait yes pd7 ne1 ne1 nce2 yes pg9 ne2 ne2 nce3 - pg10 nce4_1 nce4_1 ne3 ne3 - pg11 nce4_2 nce4_2 - pg12 ne4 ne4 - pg13 a24 a24 - pg14 a25 a25 - pb7 nadv nadv yes pe0 nbl0 nbl0 yes pe1 nbl1 nbl1 yes 1. ports f and g are not available in dev ices delivered in 100-pin packages. table 6. fsmc pin definition (continued) pins fsmc lqfp100 (1) cf cf/ide nor/psram/ sram nor/psram mux nand 16 bit
stm32f103xf, stm32f103xg memory mapping doc id 16554 rev 3 37/120 4 memory mapping the memory map is shown in figure 7 . figure 7. memory map 512-m b yte b lock 7 cortex-m 3 ' s intern a l peripher a l s 512-m b yte b lock 6 not us ed 512-m b yte b lock 5 f s mc regi s ter 512-m b yte b lock 4 f s mc ba nk 3 & ba nk4 512-m b yte b lock 3 f s mc ba nk1 & ba nk2 512-m b yte b lock 2 peripher a l s 512-m b yte b lock 1 s ram 0x0000 0000 0x1fff ffff 0x2000 0000 0x 3 fff ffff 0x4000 0000 0x5fff ffff 0x6000 0000 0x7fff ffff 0x 8 000 0000 0x9fff ffff 0xa000 0000 0xbfff ffff 0xc000 0000 0xdfff ffff 0xe000 0000 0xffff ffff 512-m b yte b lock 0 code fl as h memory ba nk 1 (512 kb) 0x0 8 0 8 0000 0x0 8 10 0000 - 0x1fff dfff 0x1fff e000- 0x1fff f7ff 0x1fff f 8 00 - 0x1fff f 8 0f 0x0 8 00 0000 0x0 8 07 ffff 0x0010 0000 - 0x07ff ffff 0x0000 0000 0x000f ffff s y s tem memory re s erved re s erved ali as ed to fl as h or s y s tem memory depending on boot pin s s ram (96 kb a li as ed b y b it- ba nding) re s erved 0x2000 0000 0x2001 7fff 0x2001 8 000 0x 3 fff ffff tim2 tim 3 0x4000 0000 - 0x4000 0 3 ff tim4 tim5 tim6 tim7 re s erved 0x4000 0400 - 0x4000 07ff 0x4000 0 8 00 - 0x4000 0bff 0x4000 0c00 - 0x4000 0fff 0x4000 1000 - 0x4000 1 3 ff 0x4000 1400 - 0x4000 17ff 0x4001 4000 - 0x4001 4bff rtc 0x4000 2 8 00 - 0x4000 2bff wwdg 0x4000 2c00 - 0x4000 2fff iwdg 0x4000 3 000 - 0x4000 33 ff re s erved 0x4000 3 400 - 0x4000 3 7ff s pi2/i2 s 2 0x4000 38 00 - 0x4000 3 bff s pi 3 /i2 s3 0x4000 3 c00 - 0x4000 3 fff re s erved 0x4000 4000 - 0x4000 4 3 ff u s art2 0x4000 4400 - 0x4000 47ff 0x4000 4 8 00 - 0x4000 4bff u s art 3 uart4 0x4000 4c00 - 0x4000 4fff uart5 0x4000 5000 - 0x4000 5 3 ff i2c1 0x4000 5400 - 0x4000 57ff i2c2 0x4000 5 8 00 - 0x4000 5bff re s erved 0x4000 6 8 00 - 0x4000 6bff bkp 0x4000 6c00 - 0x4000 6fff pwr 0x4000 7000 - 0x4000 7 3 ff dac 0x4000 7400 - 0x4000 77ff re s erved 0x4000 7 8 00 - 0x4000 ffff afio 0x4001 0000 - 0x4001 0 3 ff port a exti 0x4001 0400 - 0x4001 07ff 0x4001 0 8 00 - 0x4001 0bff port b 0x4001 0c00 - 0x4001 0fff port c 0x4001 1000 - 0x4001 1 3 ff port d 0x4001 1400 - 0x4001 17ff port e 0x4001 1 8 00 - 0x4001 1bff port f 0x4001 1c00 - 0x4001 1fff port g 0x4001 2000 - 0x4001 2 3 ff adc1 0x4001 2400 - 0x4001 27ff 0x4001 2 8 00 - 0x4001 2bff s pi1 0x4001 3 000 - 0x4001 33 ff 0x4001 3 400 - 0x4001 3 7ff u s art1 0x4001 38 00 - 0x4001 3 bff re s erved 0x4001 5 8 00 - 0x4001 7fff dma1 0x4002 0000 - 0x4002 0 3 ff dma2 0x4002 0400 - 0x4002 07ff re s erved 0x4002 0400 - 0x4002 0fff rcc 0x4002 1000 - 0x4002 1 3 ff re s erved 0x4002 1400 - 0x4002 1fff fl as h interf a ce s 1 & 2 0x4002 2000 - 0x4002 2 3 ff re s erved 0x4002 2400 - 0x4002 2fff crc 0x4002 3 000 - 0x4002 33 ff re s erved 0x4002 4400 - 0x5fff ffff f s mc ba nk1 nor/p s ram 1 0x6000 0000 - 0x6 3 ff ffff f s mc ba nk1 nor/p s ram 2 0x6400 0000 - 0x67ff ffff f s mc ba nk1 nor/p s ram 3 0x6 8 00 0000 - 0x6bff ffff f s mc ba nk1 nor/p s ram 4 0x6c00 0000 - 0x6fff ffff f s mc ba nk2 nand (nand1) 0x7000 0000 - 0x7fff ffff f s mc ba nk 3 nand (nand2) 0x 8 000 0000 - 0x 8 fff ffff f s mc ba nk4 pccard 0x9000 0000 - 0x9fff ffff f s mc regi s ter 0xa000 0000 - 0xa000 0fff re s erved 0xa000 1000 - 0xbfff ffff a i17 3 5 3 option b yte s tim 8 adc2 0x4001 8 000 - 0x4001 83 ff 0x4001 8 400 - 0x4001 ffff s dio re s erved adc 3 0x4001 3 c00 - 0x4001 3 fff tim1 0x4001 2c00 - 0x4001 2fff u s b regi s ter s s h a red u s b/can s ram 512 b yte s bxcan 0x4000 5c00 - 0x4000 5fff 0x4000 6000 - 0x4000 6 3 ff 0x4000 6400 - 0x4000 67ff fl as h memory ba nk 2 (256 kb or 512 kb) 0x0 8 0f ffff tim11 tim10 tim9 0x4001 5400 - 0x4001 57ff 0x4001 5000 - 0x4001 5 3 ff 0x4001 4c00 - 0x4001 4fff 0x4000 1 8 00 - 0x4000 1bff 0x4000 1c00 - 0x4000 1fff 0x4000 2000 - 0x4000 2 3 ff tim12 tim1 3 tim14 re s erved 0x4000 2400 - 0x4000 27ff
electrical characteristics stm32f103xf, stm32f103xg 38/120 doc id 16554 rev 3 5 electrical characteristics 5.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 5.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 5.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 2 v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 5.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 8 . 5.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 9 . figure 8. pin loading condition s figure 9. pin input voltage ai14141 c = 50 pf stm32f103xx pin ai14142 stm32f103xx pin v in
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 39/120 5.1.6 power supply scheme figure 10. power supply scheme caution: in figure 10 , the 4.7 f capacitor must be connected to v dd3 . 5.1.7 current con sumption measurement figure 11. current consumption measurement scheme ai 6 $$ !n alo g 2#s0,, 0o werswi tch 6 "!4 '0 )/ s /54 ). +ernellogic #05 $igital -emories "ackupcircuitry /3#+24# "ackupregisters 7ake uplogic n& ?& 6 2egulator 6 33 6 $$! 6 2%& 6 2%& 6 33! !$# $!# ,evelshifter )/ ,ogic 6 $$ n& ?& 6 2%& n& ?& 6 $$ ai14126 v bat v dd v dda i dd _v bat i dd
electrical characteristics stm32f103xf, stm32f103xg 40/120 doc id 16554 rev 3 5.2 absolute maximum ratings stresses above the absolute maximum ratings listed in ta bl e 7: voltage characteristics , ta bl e 8: current characteristics , and ta bl e 9: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 7. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda and v dd ) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ?0.3 4.0 v v in (2) 2. v in maximum must always be respected. refer to table 8: current characteristics for the maximum allowed injected current values. input voltage on five volt tolerant pin v ss ? 0.3 v dd + 4.0 input voltage on any other pin v ss ? 0.3 4.0 | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins - 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 5.3.12: absolute maximum ratings (electrical sensitivity) table 8. current characteristics symbol ratings max. unit i vdd total current into v dd /v dda power lines (source) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 150 ma i vss total current out of v ss ground lines (sink) (1) 150 i io output current sunk by any i/o and control pin 25 output current source by any i/os and control pin ? 25 i inj(pin) (2) 2. negative injection disturbs the analog per formance of the device. see note 3 below table 65 on page 103 . injected current on five volt tolerant pins (3) 3. positive injection is not possible on thes e i/os. a negative injection is induced by v in v dd while a negative injection is induced by v in stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 41/120 5.3 operating conditions 5.3.1 general operating conditions table 9. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 150 c table 10. general operating conditions symbol parameter co nditions min max unit f hclk internal ahb clock frequency 0 72 mhz f pclk1 internal apb1 clock frequency 0 36 f pclk2 internal apb2 clock frequency 0 72 v dd standard operating voltage 2 3.6 v v dda (1) 1. when the adc is used, refer to table 62: adc characteristics . analog operating voltage (adc not used) must be the same potential as v dd (2) 2. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and operation. 23.6 v analog operating voltage (adc used) 2.4 3.6 v bat backup operating voltage 1.8 3.6 v p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (3) 3. if t a is lower, higher p d values are allowed as long as t j does not exceed t j max (see table 6.2: thermal characteristics on page 114 ). lqfp144 - 666 mw lqfp100 - 434 lqfp64 - 444 lfbga144 - 500 wlcsp64 - 400 t a ambient temperature for 6 suffix version maximum power dissipation ?40 85 c low power dissipation (4) 4. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t j max (see table 6.2: thermal characteristics on page 114 ). ?40 105 ambient temperature for 7 suffix version maximum power dissipation ?40 105 c low power dissipation (4) ?40 125 t j junction temperature range 6 suffix version ?40 105 c 7 suffix version ?40 125
electrical characteristics stm32f103xf, stm32f103xg 42/120 doc id 16554 rev 3 5.3.2 operating conditions at power-up / power-down the parameters given in ta bl e 11 are derived from tests performed under the ambient temperature condition summarized in ta b l e 10 . table 11. operating conditions at power-up / power-down 5.3.3 embedded reset and power control block characteristics the parameters given in ta bl e 12 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 10 . symbol parameter conditions min max unit t vdd v dd rise time rate 0 s/v v dd fall time rate 20 table 12. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.1 2.18 2.26 v pls[2:0]=000 (falling edge) 2 2.08 2.16 v pls[2:0]=001 (rising edge) 2.19 2.28 2.37 v pls[2:0]=001 (falling edge) 2.09 2.18 2.27 v pls[2:0]=010 (rising edge) 2.28 2.38 2.48 v pls[2:0]=010 (falling edge) 2.18 2.28 2.38 v pls[2:0]=011 (rising edge) 2.38 2.48 2.58 v pls[2:0]=011 (falling edge) 2.28 2.38 2.48 v pls[2:0]=100 (rising edge) 2.47 2.58 2.69 v pls[2:0]=100 (falling edge) 2.37 2.48 2.59 v pls[2:0]=101 (rising edge) 2.57 2.68 2.79 v pls[2:0]=101 (falling edge) 2.47 2.58 2.69 v pls[2:0]=110 (rising edge) 2.66 2.78 2.9 v pls[2:0]=110 (falling edge) 2.56 2.68 2.8 v pls[2:0]=111 (rising edge) 2.76 2.88 3 v pls[2:0]=111 (falling edge) 2.66 2.78 2.9 v v pvdhyst (2) pvd hysteresis - 100 - mv v por/pdr power on/power down reset threshold falling edge 1.8 (1) 1. the product behavior is guaranteed by design down to the minimum v por/pdr value. 1.88 1.96 v rising edge 1.84 1.92 2.0 v v pdrhyst (2) pdr hysteresis - 40 - mv t rsttempo (2) 2. guaranteed by design, not tested in production. reset temporization 1 2.5 4.5 ms
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 43/120 5.3.4 embedded reference voltage the parameters given in ta bl e 13 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 10 . 5.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pin loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 11: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to dhrystone 2.1 code. maximum current consumption the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled except when explicitly mentioned the flash memory access time is adjusted to the f hclk frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states above) prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) when the peripherals are enabled f pclk1 = f hclk /2, f pclk2 = f hclk the parameters given in ta bl e 14 , ta bl e 15 and ta bl e 16 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 10 . table 13. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.16 1.20 1.26 v ?40 c < t a < +85 c 1.16 1.20 1.24 v t s_vrefint (1) 1. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the internal reference voltage -5.1 17.1 (2) 2. guaranteed by design, not tested in production. s v rerint (2) internal reference voltage spread over the temperature range v dd = 3 v 10 mv - - 10 mv t coeff (2) temperature coefficient - - 100 ppm/c
electrical characteristics stm32f103xf, stm32f103xg 44/120 doc id 16554 rev 3 table 14. maximum current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk max (1) 1. based on characterization , not tested in production. unit t a = 85 c t a = 105 c i dd supply current in run mode external clock (2) , all peripherals enabled 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 72 mhz 68 69 ma 48 mhz 51 51 36 mhz 41 41 24 mhz 29 30 16 mhz 22 22.5 8 mhz 12.5 14 external clock (3) , all peripherals disabled 72 mhz 39 39 48 mhz 29.5 30 36 mhz 24 24.5 24 mhz 17.5 19 16 mhz 14 15 8 mhz 8.5 10.5 table 15. maximum current consumption in run mode, code with data processing running from ram symbol parameter conditions f hclk max (1) 1. data based on characterization results, tested in production at v dd max, f hclk max. unit t a = 85 c t a = 105 c i dd supply current in run mode external clock (2) , all peripherals enabled 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 72 mhz 65 65.5 ma 48 mhz 46.5 47 36 mhz 37 37 24 mhz 26.5 27 16 mhz 19 20 8 mhz 11.5 13 external clock (3) , all peripherals disabled 72 mhz 34.5 36 48 mhz 25 26 36 mhz 20.5 21 24 mhz 15 16 16 mhz 11 13 8 mhz 7.5 9
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 45/120 figure 12. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals enabled figure 13. typical current consumption in run mode versus frequency (at 3.6 v)- code with data processing running from ram, peripherals disabled ai #onsumptionm! 4emperature?# -(z -(z -(z -(z -(z -(z #onsumptionm! 4emperature?# -(z -(z -(z -(z -(z -(z ai
electrical characteristics stm32f103xf, stm32f103xg 46/120 doc id 16554 rev 3 table 16. maximum current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk max (1) 1. based on characterization, tested in production at v dd max, f hclk max with peripherals enabled. unit t a = 85 c t a = 105 c i dd supply current in sleep mode external clock (2) , all peripherals enabled 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 72 mhz 47.5 48.5 ma 48 mhz 34 35 36 mhz 27.5 27.5 24 mhz 20 20.5 16 mhz 15 16 8 mhz 9 11 external clock (3) , all peripherals disabled 72 mhz 9.5 11.2 48 mhz 7.7 9.5 36 mhz 6.9 8.5 24 mhz 5.9 7.8 16 mhz 5.4 7.2 8 mhz 4.7 6.4
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 47/120 figure 14. typical current consumption on v bat with rtc on vs. temperature at different v bat values table 17. typical and maximum current consumptions in stop and standby modes symbol parameter conditions typ (1) max unit v dd /v bat = 2.0 v v dd /v bat = 2.4 v v dd /v bat = 3.3 v t a = 85 c t a = 105 c i dd supply current in stop mode regulator in run mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog), f ck =8 mhz 44.8 45.3 46.4 810 1680 a regulator in low-power mode, low- speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 37.4 37.8 38.7 790 1660 supply current in standby mode low-speed internal rc oscillator and independent watchdog off, low-speed oscillator and rtc off 1.8 2.0 2.5 5 (2) 8 (2) i dd_vbat backup domain supply current low-speed oscillator and rtc on 1.05 1.1 1.4 2 (2) 2.3 (2) 1. typical values are measured at t a = 25 c. 2. based on characterization, not tested in production. 0 0.5 1 1.5 2 2.5 ?45 25 8 5105 temper a t u re (c) con su mption ( a) 1. 8 v 2 v 2.4 v 3 . 3 v 3 .6 v a i17 33 7
electrical characteristics stm32f103xf, stm32f103xg 48/120 doc id 16554 rev 3 figure 15. typical current consumption in stop mode with regulator in run mode versus temperature at different v dd values # # # # #onsumption ! 4emperature?# 6 6 6 6 6 ai
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 49/120 figure 16. typical current consumption in stop mode with regulator in low-power mode versus temperature at different v dd values figure 17. typical current consumption in standby mode versus temperature at different v dd values # # # # #onsumption ! 4emperature?# 6 6 6 6 6 ai # # # # #onsumption ! 4emperature?# 6 6 6 6 6 ai
electrical characteristics stm32f103xf, stm32f103xg 50/120 doc id 16554 rev 3 typical current consumption the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load). all peripherals are disabled except if it is explicitly mentioned. the flash access time is adjusted to f hclk frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states above). ambient temperature and v dd supply voltage conditions summarized in table 10 . prefetch is on (reminder: this bit must be set before clock setting and bus prescaling) when the peripherals are enabled f pclk1 = f hclk /4, f pclk 2 = f hclk /2, f adcclk = f pclk2 /4 table 18. typical current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ (1) 1. typical values are measures at t a = 25 c, v dd = 3.3 v. unit all peripherals enabled (2) 2. add an additional power consumption of 0.8 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). all peripherals disabled i dd supply current in run mode external clock (3) 3. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 72 mhz 52.5 33.5 ma 48 mhz 36.6 23.8 36 mhz 28.5 18.7 24 mhz 24.1 12.8 16 mhz 14 9.2 8 mhz 7.7 5.4 4 mhz 4.6 3.4 2 mhz 3 2.3 1 mhz 2.2 1.8 500 khz 1.7 1.5 125 khz 1.4 1.3 running on high speed internal rc (hsi), ahb prescaler used to reduce the frequency 64 mhz 45.5 28.6 ma 48 mhz 35.1 22.4 36 mhz 27.5 17.5 24 mhz 18.9 11.6 16 mhz 12.2 8.2 8 mhz 7.2 4.8 4 mhz 4 2.7 2 mhz 2.3 1.7 1 mhz 1.5 1.2 500 khz 1.1 0.9 125 khz 0.75 0.7
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 51/120 table 19. typical current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk typ (1) 1. typical values are measures at t a = 25 c, v dd = 3.3 v. unit all peripherals enabled (2) 2. add an additional power consumption of 0.8 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). all peripherals disabled i dd supply current in sleep mode external clock (3) 3. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 72 mhz 32.5 7 ma 48 mhz 23 5 36 mhz 17.7 4 24 mhz 12.2 3.1 16 mhz 8.4 2.3 8 mhz 4.6 1.5 4 mhz 3 1.3 2 mhz 2.15 1.25 1 mhz 1.7 1.2 500 khz 1.5 1.15 125 khz 1.35 1.15 running on high speed internal rc (hsi), ahb prescaler used to reduce the frequency 64 mhz 28.7 5.7 48 mhz 22 4.4 36 mhz 17 3.35 24 mhz 11.6 2.3 16 mhz 7.7 1.6 8 mhz 3.9 0.8 4 mhz 2.3 0.7 2 mhz 1.5 0.6 1 mhz 1.1 0.5 500 khz 0.9 0.5 125 khz 0.7 0.5
electrical characteristics stm32f103xf, stm32f103xg 52/120 doc id 16554 rev 3 on-chip peripheral current consumption the current consumption of the on-chip peripherals is given in ta bl e 20 . the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ambient operating temperature and v dd supply voltage conditions summarized in ta bl e 7 table 20. peripheral current consumption (1) peripheral typical consumption at 25 c unit apb1 tim2 1.6 ma tim3 1.5 tim4 1.5 tim5 1.5 tim6 0.6 tim7 0.6 tim12 0.95 tim13 0.7 tim14 0.75 spi2 0.6 spi3 0.6 usart2 0.7 usart3 0.7 usart4 0.7 usart5 0.7 i2c1 0.65 i2c2 0.65 usb 0.9 can 0.9 dac (2) 1.35
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 53/120 5.3.6 external cloc k source characteristics high-speed external user clock generated from an external source the characteristics given in ta b l e 21 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in ta b l e 10 . apb2 gpioa 0.55 ma gpiob 0.55 gpioc 0.55 gpiod 0.6 gpioe 0.6 gpiof 0.55 gpiog 0.55 tim1 1.95 tim8 1.9 tim9 1 tim10 0.8 tim11 0.8 adc1 (3) 1.85 adc2 (3) 1.8 adc3 (3) 1.8 spi1 0.45 usart1 0.8 1. f hclk = 72 mhz, f apb1 = f hclk /2, f apb2 = f hclk , default prescaler value for each peripheral. 2. specific conditions for dac: en1, en2 bits in the dac_cr register are set to 1 and the converted value set to 0x800. 3. specific conditions for adc: f hclk = 56 mhz, f apb1 = f hclk/2 , f apb2 = f hclk , f adcclk = f apb2 /4, adon bit in the adc_cr2 register is set to 1. table 20. peripheral current consumption (1) (continued) peripheral typical consumption at 25 c unit
electrical characteristics stm32f103xf, stm32f103xg 54/120 doc id 16554 rev 3 low-speed external user clock generated from an external source the characteristics given in ta b l e 22 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in ta b l e 10 . table 21. high-speed external user clock characteristics symbol parameter conditions min typ max unit f hse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. 1825mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 5- - ns t r(hse) t f(hse) osc_in rise or fall time (1) --20 c in(hse) osc_in input capacitance (1) -5-pf ducy (hse) duty cycle 45 - 55 % i l osc_in input leakage current v ss v in v dd --1a table 22. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lse) t w(lse) osc32_in high or low time (1) 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time (1) --50 c in(lse) osc32_in input capacitance (1) -5 -pf ducy (lse) duty cycle 30 - 70 % i l osc32_in input leakage current v ss v in v dd --1a
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 55/120 figure 18. high-speed external clock source ac timing diagram figure 19. low-speed external clock source ac timing diagram ai14143 os c _i n exter nal stm32f103xx clo ck so urc e v hseh t f(hse) t w(hse) i l 90% 10% t hse t t r(hse) t w(hse) f hse_ext v hsel ai14144b osc32_in exter nal stm32f103xx clo ck so urc e v lseh t f(lse) t w(lse) i l 90% 10% t lse t t r(lse) t w(lse) f lse_ext v lsel
electrical characteristics stm32f103xf, stm32f103xg 56/120 doc id 16554 rev 3 high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 16 mhz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 23 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 20 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . refer to the application note an28 67 ?oscillator design guide for st microcontrollers? available fr om the st website www.st.com. figure 20. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. table 23. hse 4-16 mhz oscillator characteristics (1)(2) 1. resonator characte ristics given by the crystal/ ceramic resonator manufacturer. 2. based on characterization results, not tested in production. symbol parameter conditions min typ max unit f osc_in oscillator frequency 4 8 16 mhz r f feedback resistor - 200 - k c recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (3) 3. the relatively low value of the rf resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and t he bias condition change. however, it is recommended to take this point into account if the mcu is used in tough humidity conditions. r s = 30 -30-pf i 2 hse driving current v dd = 3.3 v, v in = v ss with 30 pf load --1ma g m oscillator transconductance startup 25 - ma/v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonat or and it can vary significantly with the crystal manufacturer startup time v dd is stabilized - 2 - ms ai14145 osc_ou t osc_in f hse c l1 r f stm32f103xx 8 mh z resonator r ext (1) c l2 resonator with integrated capacitors bias controlled gain
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 57/120 low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 24 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). note: for c l1 and c l2 , it is recommended to use high-quality ceramic capacitors in the 5 pf to 15 pf range selected to match the requirements of the crystal or resonator (see figure 21 ). c l1 and c l2, are usually the same size. the crystal ma nufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . load capacitance c l has the following formula: c l = c l1 x c l2 / ( c l1 + c l2 ) + c stray where c stray is the pin capacitance and board or trace pcb-related capacitance. typically, it is between 2 pf and 7 pf. caution: to avoid exceeding the maximum value of c l1 and c l2 (15 pf) it is strongly recommended to use a resonator with a load capacitance c l 7 pf. never use a resonator with a load capacitance of 12.5 pf. example: if you choose a resonator with a load capacitance of c l = 6 pf, and c stray = 2 pf, then c l1 = c l2 = 8 pf. table 24. lse oscillator characteristics (f lse = 32.768 khz) (1)(2) symbol parameter conditions min typ max unit r f feedback resistor - 5 - m c (2) recommended load capacitance versus equivalent serial resistance of the crystal (r s ) r s = 30 k - - 15 pf i 2 lse driving current v dd = 3.3 v, v in = v ss --1.4a g m oscillator transconductance 5 - - a/v t su(lse) (3) startup time v dd is stabilized t a = 50 c - 1.5 - s t a = 25 c - 2.5 - t a = 10 c - 4 - t a = 0 c - 6 - t a = -10 c - 10 - t a = -20 c - 17 - t a = -30 c - 32 - t a = -40 c - 60 - 1. based on characterization, not tested in production. 2. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 3. t su(lse) is the startup time measured from the moment it is enabled (by software) until a st abilized 32.768 khz oscillation is reached. this value is measured for a standard crystal and it can vary significantly with the crystal manufacturer, pcb layout and humidity
electrical characteristics stm32f103xf, stm32f103xg 58/120 doc id 16554 rev 3 figure 21. typical application with a 32.768 khz crystal 5.3.7 internal clock source characteristics the parameters given in ta bl e 25 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 10 . high-speed internal (hsi) rc oscillator ai14146 osc32_ou t osc32_in f lse c l1 r f stm32f103xx 32.768 kh z resonator c l2 resonator with integrated capacitors bias controlled gain table 25. hsi oscillator characteristics (1) 1. v dd = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - 8 mhz ducy (hsi) duty cycle 45 - 55 % acc hsi accuracy of the hsi oscillator user-trimmed with the rcc_cr register (2) 2. refer to application note an2868 ?stm32f10xxx internal rc oscillator (hsi) calibration? available from the st website www.st.com. --1 (3) 3. guaranteed by design, not tested in production. % factory- calibrated (4) 4. based on characterization , not tested in production. t a = ?40 to 105 c ?2 - 2.5 % t a = ?10 to 85 c ?1.5 - 2.2 % t a = 0 to 70 c ?1.3 - 2 % t a = 25 c ?1.1 - 1.8 % t su(hsi) (4) hsi oscillator startup time 1-2s i dd(hsi) (4) hsi oscillator power consumption - 80 100 a
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 59/120 low-speed internal (lsi) rc oscillator wakeup time from low-power mode the wakeup times given in ta b l e 27 is measured on a wakeup phase with a 8-mhz hsi rc oscillator. the clock source used to wake up the device depe nds from the current operating mode: stop or standby mode: the cloc k source is the rc oscillator sleep mode: the clock source is the clock that was set before entering sleep mode. all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 10 . table 26. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi (2) 2. based on characterization , not tested in production. frequency 30 40 60 khz t su(lsi) (3) 3. guaranteed by design, not tested in production. lsi oscillator startup time - - 85 s i dd(lsi) (3) lsi oscillator power consumption - 0.65 1.2 a table 27. low-power mode wakeup timings symbol parameter typ unit t wusleep (1) 1. the wakeup times are measured from the wakeup even t to the point in which the user application code reads the first instruction. wakeup from sleep mode 1.8 s t wustop (1) wakeup from stop mode (regulator in run mode) 3.6 s wakeup from stop mode (regulator in low power mode) 5.4 t wustdby (1) wakeup from standby mode 50 s
electrical characteristics stm32f103xf, stm32f103xg 60/120 doc id 16554 rev 3 5.3.8 pll characteristics the parameters given in ta bl e 28 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 10 . 5.3.9 memory characteristics flash memory the characteristics are given at t a = ?40 to 105 c unless otherwise specified. table 28. pll characteristics symbol parameter value unit min typ max (1) 1. based on characterization , not tested in production. f pll_in pll input clock (2) 2. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . 18.0 25 mhz pll input clock duty cycle 40 - 60 % f pll_out pll multiplier output clock 16 - 72 mhz t lock pll lock time - - 200 s jitter cycle-to-cycle jitter - - 300 ps table 29. flash memory characteristics symbol parameter conditions min typ max (1) 1. guaranteed by design, not tested in production. unit t prog 16-bit programming time t a = ?40 to +105 c 40 52.5 70 s t erase page (2 kb) erase time t a = ?40 to +105 c 20 - 40 ms t me mass erase time t a = ?40 to +105 c 20 - 40 ms i dd supply current read mode f hclk = 72 mhz with 2 wait states, v dd = 3.3 v --28ma write mode f hclk = 72 mhz, v dd = 3.3 v --7ma erase mode f hclk = 72 mhz, v dd = 3.3 v --5ma power-down mode / halt, v dd = 3.0 to 3.6 v - - 50 a v prog programming voltage 2 - 3.6 v
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 61/120 5.3.10 fsmc characteristics asynchronous waveforms and timings figure 22 through figure 25 represent asynchronous waveforms and ta b l e 31 through ta bl e 35 provide the corresponding timings. the results shown in these tables are obtained with the following fsmc configuration: addresssetuptime = 0 addressholdtime = 1 datasetuptime = 1 note: on all tables, the t hclk is the hclk clock period. table 30. flash memory endurance and data retention symbol parameter conditions value unit min (1) 1. based on characterization not tested in production. n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over t he whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20
electrical characteristics stm32f103xf, stm32f103xg 62/120 doc id 16554 rev 3 figure 22. asynchronous non-multiplexed sram/psram/nor read waveforms 1. mode 2/b, c and d only. in mode 1, fsmc_nadv is not used. note: fsmc_busturnaroundduration = 0. $ata &3-#?.% &3-#?.",;= &3-#?$;= t v",?.% t h$ata?.% &3-#?./% !ddress &3-#?!;= t v!?.% &3-#?.7% t su$ata?.% t w.% -36 w./% t t v./%?.% t h.%?./% t h$ata?./% t h!?./% t h",?./% t su$ata?./% &3-#?.!$6 t v.!$6?.% t w.!$6
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 63/120 figure 23. asynchronous non-multiplexed sram/psram/nor write waveforms 1. mode 2/b, c and d only. in mode 1, fsmc_nadv is not used. table 31. asynchronous non-multiplexed sram/psram/nor read timings (1) 1. c l = 15 pf. symbol parameter min max unit t w(ne) fsmc_ne low time 5t hclk + 0.5 5t hclk + 2 ns t v(noe_ne) fsmc_nex low to fsmc_noe low 0.5 1.5 ns t w(noe) fsmc_noe low time 5t hclk ? 1 5t hclk + 1 ns t h(ne_noe) fsmc_noe high to fsmc_ne high hold time 0 - ns t v(a_ne) fsmc_nex low to fsmc_a valid - 3 ns t h(a_noe) address hold time after fsmc_noe high 0 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 0 ns t h(bl_noe) fsmc_bl hold time after fsmc_noe high 0.5 - ns t su(data_ne) data to fsmc_nex high setup time 2t hclk - 1 - ns t su(data_noe) data to fsmc_noex high setup time 2t hclk - 1 - ns t h(data_noe) data hold time after fsmc_noe high 0 - ns t h(data_ne) data hold time after fsmc_nex high 0 - ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low - 0 ns t w(nadv) fsmc_nadv low time - t hclk + 2 ns nbl data fsmc_nex fsmc_nbl[3:0] fsmc_d[15:0] t v(bl_ne) t h(data_nwe) fsmc_noe address fsmc_a[25:0] t v(a_ne) t w(nwe) fsmc_nwe t v(nwe_ne) t h(ne_nwe) t h(a_nwe) t h(bl_nwe) t v(data_ne) t w(ne) ai14990 fsmc_nadv (1) t v(nadv_ne) t w(nadv)
electrical characteristics stm32f103xf, stm32f103xg 64/120 doc id 16554 rev 3 table 32. asynchronous non-multiplexed sram/psram/nor write timings (1) 1. c l = 15 pf. symbol parameter min max unit t w(ne) fsmc_ne low time 3t hclk + 0.5 3t hclk + 1.5 ns t v(nwe_ne) fsmc_nex low to fsmc_nwe low t hclk + 0.5 t hclk + 1.5 ns t w(nwe) fsmc_nwe low time t hclk ? 0.5 t hclk + 1 ns t h(ne_nwe) fsmc_nwe high to fsmc_ne high hold time t hclk ? 0.5 - ns t v(a_ne) fsmc_nex low to fsmc_a valid - 0 ns t h(a_nwe) address hold time after fsmc_nwe high t hclk -ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 1.5 ns t h(bl_nwe) fsmc_bl hold time after fsmc_nwe high t hclk ? 1.5 - ns t v(data_ne) fsmc_nex low to data valid - t hclk ns t h(data_nwe) data hold time afte r fsmc_nwe high t hclk -ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low - 0 ns t w(nadv) fsmc_nadv low time - t hclk + 1.5 ns table 33. asynchronous read muxed symbol parameter min max unit t w(ne) fsmc_ne low time 7t hclk + 0.5 7t hclk + 2 ns t v(noe_ne) fsmc_nex low to fsmc_noe low 3t hclk + 0.5 3t hclk + 1.5 t w(noe) fsmc_noe low time 4t hclk ? 1 4t hclk + 1 t h(ne_noe) fsmc_noe high to fsmc_ne high hold time 0.5 - t v(a_ne) fsmc_nex low to fsmc_a valid - 0 t v(nadv_ne) fsmc_nex low to fsmc_nadv low 0 1 t w(nadv) fsmc_nadv low time t hclk + 0.5 t hclk + 2 t h(ad_nadv) fsmc_ad (address) valid hold time after fsmc nadv high t hclk - t h(a_noe) address hold time after fsmc_noe high t hclk ? 2 - t h(bl_noe) fsmc_bl time after fsmc_noe high 0.5 - t v(bl_ne) fsmc_nex low to fsmc_bl valid - 0 t su(data_ne) data to fsmc_nex high setup time 4t hclk ? 0.5 - t su(data_noe) data to fsmc_noe high setup time 4t hclk ? 1 - t h(data_ne) data hold time after fsmc_nex high 0 - t h(data_noe) data hold time afte r fsmc_noe high 0 -
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 65/120 figure 24. asynchronous multiplexed psram/nor read waveforms table 34. asynchronous multiplexed psram/nor read timings (1) 1. c l = 15 pf. symbol parameter min max unit t w(ne) fsmc_ne low time 7t hclk + 0.5 7t hclk + 2 ns t v(noe_ne) fsmc_nex low to fsmc_noe low 3t hclk + 0.5 3t hclk + 1.5 ns t w(noe) fsmc_noe low time 4t hclk ? 1 4t hclk + 1 ns t h(ne_noe) fsmc_noe high to fsmc_ne high hold time 0.5 - ns t v(a_ne) fsmc_nex low to fsmc_a valid - 0 ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low 0 1 ns t w(nadv) fsmc_nadv low time t hclk + 0.5 t hclk + 2 ns t h(ad_nadv) fsmc_ad (address) valid hold time after fsmc_nadv high t hclk - ns t h(a_noe) address hold time after fsmc_noe high t hclk -2 - ns t h(bl_noe) fsmc_bl hold time after fsmc_noe high 0.5 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 0 ns t su(data_ne) data to fsmc_nex high setup time 4t hclk - 0.5 - ns t su(data_noe) data to fsmc_noe high setup time 4t hclk - 1 - ns t h(data_ne) data hold time after fsmc_nex high 0 - ns t h(data_noe) data hold time after fsmc_noe high 0 - ns nbl data fsmc_nbl[1:0] fsmc_ ad[15:0] t v(bl_ne) t h(data_ne) address fsmc_a[25:16] t v(a_ne) fsmc_nwe t v(a_ne) ai14892b address fsmc_nadv t v(nadv_ne) t w(nadv) t su(data_ne) t h(ad_nadv) fsmc_ne fsmc_noe t w(ne) t w(noe) t v(noe_ne) t h(ne_noe) t h(a_noe) t h(bl_noe) t su(data_noe) t h(data_noe)
electrical characteristics stm32f103xf, stm32f103xg 66/120 doc id 16554 rev 3 figure 25. asynchronous multiplexed psram/nor write waveforms table 35. asynchronous multiplexed psram/nor write timings (1) 1. c l = 15 pf. symbol parameter min max unit t w(ne) fsmc_ne low time 5t hclk + 0.5 5t hclk + 2 ns t v(nwe_ne) fsmc_nex low to fsmc_nwe low t hclk + 1 t hclk + 1.5 ns t w(nwe) fsmc_nwe low time 3t hclk + 0.5 3t hclk + 1 ns t h(ne_nwe) fsmc_nwe high to fsmc_ne high hold time t hclk ? 0.5 - ns t v(a_ne) fsmc_nex low to fsmc_a valid - 3.5 ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low 0 1 ns t w(nadv) fsmc_nadv low time t hclk + 0.5 t hclk + 1.5 ns t h(ad_nadv) fsmc_ad (address) valid hold time after fsmc_nadv high t hclk ? 0.5 - ns t h(a_nwe) address hold time after fsmc_nwe high 4t hclk ? 2 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 0.5 ns t h(bl_nwe) fsmc_bl hold time after fsmc_nwe high t hclk ? 1.5 - ns t v(data_nadv) fsmc_nadv high to data valid - t hclk + 6 ns t h(data_nwe) data hold time after fsmc_nwe high t hclk ? 0.5 - ns nbl data fsmc_nex fsmc_nbl[1:0] fsmc_ ad[15:0] t v(bl_ne) t h(data_nwe) fsmc_noe address fsmc_a[25:16] t v(a_ne) t w(nwe) fsmc_nwe t v(nwe_ne) t h(ne_nwe) t h(a_nwe) t h(bl_nwe) t v(a_ne) t w(ne) ai14891b address fsmc_nadv t v(nadv_ne) t w(nadv) t v(data_nadv) t h(ad_nadv)
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 67/120 synchronous waveforms and timings figure 26 through figure 29 represent synchronous waveforms and ta bl e 37 through ta bl e 39 provide the corresponding timings. the results shown in these tables are obtained with the following fsmc configuration: burstaccessmode = fsmc_burstaccessmode_enable; memorytype = fsmc_memorytype_cram; writeburst = fsmc_writeburst_enable; clkdivision = 1; (0 is not supported, see the stm32f10xxx reference manual) datalatency = 1 for nor flash; datalatency = 0 for psram figure 26. synchronous multiplexed nor/psram read timings &3-#?#,+ &3-#?.%x &3-#?.!$6 &3-#?!;= &3-#?./% &3-#?!$;= !$;= $ $ &3-#?.7!)4 7!)4#&'b7!)40/,b &3-#?.7!)4 7!)4#&'b7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, t d#,+, .%x( t d#,+, .!$6, t d#,+, !6 t d#,+, .!$6( t d#,+, !)6 t d#,+, ./%, t d#,+, ./%( t d#,+, !$6 t d#,+, !$)6 t su!$6 #,+( t h#,+( !$6 t su!$6 #,+( t h#,+( !$6 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 aih $
electrical characteristics stm32f103xf, stm32f103xg 68/120 doc id 16554 rev 3 table 36. synchronous multiplexed nor/psram read timings (1) 1. c l = 15 pf. symbol parameter min max unit t w(clk) fsmc_clk period 27.6 - ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x = 0...2) - 0.5 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x = 0...2) 1 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 1 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 0.5 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x = 0...25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x = 16...25) 1.5 - ns t d(clkl-noel) fsmc_clk low to fsmc_noe low - 14 ns t d(clkl-noeh) fsmc_clk low to fsmc_noe high 1 - ns t d(clkl-adv) fsmc_clk low to fsmc_ad[15:0] valid - 11 ns t d(clkl-adiv) fsmc_clk low to fsmc_ad[15:0] invalid 0.5 - ns t su(adv-clkh) fsmc_a/d[15:0] valid data before fsmc_clk high 2- ns t h(clkh-adv) fsmc_a/d[15:0] valid data after fsmc_clk high 0 - ns
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 69/120 figure 27. synchronous multiplexed psram write timings &3-#?#,+ &3-#?.%x &3-#?.!$6 &3-#?!;= &3-#?.7% &3-#?!$;= !$;= $ $ &3-#?.7!)4 7!)4#&'b7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, t d#,+, .%x( t d#,+, .!$6, t d#,+, !6 t d#,+, .!$6( t d#,+, !)6 t d#,+, .7%( t d#,+, .7%, t d#,+, .",( t d#,+, !$6 t d#,+, !$)6 t d#,+, $ata t su.7!)46 #,+( t h#,+( .7!)46 aig t d#,+, $ata &3-#?.",
electrical characteristics stm32f103xf, stm32f103xg 70/120 doc id 16554 rev 3 table 37. synchronous multiplexed psram write timings (1) 1. c l = 15 pf. symbol parameter min max unit t w(clk) fsmc_clk period 27.5 - ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x = 0...2) - 0 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x = 0...2) 1 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 1 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 1 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x = 16...25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x = 16...25) 1 - ns t d(clkl-nwel) fsmc_clk low to fsmc_nwe low - 1 ns t d(clkl-nweh) fsmc_clk low to fsmc_nwe high 1.5 - ns t d(clkl-adv) fsmc_clk low to fsmc_ad[15:0] valid - 10 ns t d(clkl-adiv) fsmc_clk low to fsmc_ad[15:0] invalid 1 - ns t d(clkl-data) fsmc_a/d[15:0] valid after fsmc_clk low - 6 ns t d(clkl-nblh) fsmc_clk low to fsmc_nbl high 1 - ns
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 71/120 figure 28. synchronous non-multiplexed nor/psram read timings table 38. synchronous non-multiplexed nor/psram read timings (1) 1. c l = 15 pf. symbol parameter min max unit t w(clk) fsmc_clk period 27.6 - ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x = 0...2) - 1.5 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x = 0...2) 2 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 0.5 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 1 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x = 0...25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x = 0...25) 2 - ns t d(clkl-noel) fsmc_clk low to fsmc_noe low - t hclk + 1 ns t d(clkl-noeh) fsmc_clk low to fsmc_noe high 1.5 - ns t su(dv-clkh) fsmc_d[15:0] valid data bef ore fsmc_clk high 3.5 - ns t h(clkh-dv) fsmc_d[15:0] valid data after fsmc_clk high 0 - ns &3-#?#,+ &3-#?.%x &3-#?!;= &3-#?./% &3-#?$;= $ $ &3-#?.7!)4 7!)4#&'b7!)40/,b &3-#?.7!)4 7!)4#&'b7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, t d#,+, .%x( t d#,+, !6 t d#,+, !)6 t d#,+, ./%, t d#,+, ./%( t su$6 #,+( t h#,+( $6 t su$6 #,+( t h#,+( $6 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 aig &3-#?.!$6 t d#,+, .!$6, t d#,+, .!$6( $
electrical characteristics stm32f103xf, stm32f103xg 72/120 doc id 16554 rev 3 figure 29. synchronous non-multiplexed psram write timings table 39. synchronous non-multiplexed psram write timings (1) 1. c l = 15 pf. symbol parameter min max unit t w(clk) fsmc_clk period 27.6 - ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x = 0...2) - 0.5 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x = 0...2) 1.5 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 1 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 0.5 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x = 16...25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x = 16...25) 1.5 - ns t d(clkl-nwel) fsmc_clk low to fsmc_nwe low - 1 ns t d(clkl-nweh) fsmc_clk low to fsmc_nwe high 1.5 - ns t d(clkl-data) fsmc_d[15:0] valid data after fsmc_clk low - 2.5 ns t d(clkl-nblh) fsmc_clk low to fsmc_nbl high 0.5 - ns &3-#?#,+ &3-#?.%x &3-#?!;= &3-#?.7% &3-#?$;= $ $ &3-#?.7!)4 7!)4#&'b7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, t d#,+, .%x( t d#,+, !6 t d#,+, !)6 t d#,+, .7%( t d#,+, .7%, t d#,+, $ata t su.7!)46 #,+( t h#,+( .7!)46 aih &3-#?.!$6 t d#,+, .!$6, t d#,+, .!$6( t d#,+, $ata &3-#?.", t d#,+, .",(
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 73/120 pc card/compactflash controller waveforms and timings figure 30 through figure 35 represent synchronous waveforms and ta bl e 42 provides the corresponding timings. the results shown in th is table are obtained with the following fsmc configuration: com.fsmc_setuptime = 0x04; com.fsmc_waitsetuptime = 0x07; com.fsmc_holdsetuptime = 0x04; com.fsmc_hizsetuptime = 0x00; att.fsmc_setuptime = 0x04; att.fsmc_waitsetuptime = 0x07; att.fsmc_holdsetuptime = 0x04; att.fsmc_hizsetuptime = 0x00; io.fsmc_setuptime = 0x04; io.fsmc_waitsetuptime = 0x07; io.fsmc_holdsetuptime = 0x04; io.fsmc_hizsetuptime = 0x00; tclrsetuptime = 0; tarsetuptime = 0; figure 30. pc card/compactflash controller waveforms for common memory read access 1. fsmc_nce4_2 remains high (inactive during 8-bit access. fsmc_nwe t w(noe) fsmc_n oe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_2 (1) fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nce4_1-noe) t su(d-noe) t h(noe-d) t v(ncex-a) t d(nreg-ncex) t d(niord-ncex) t h(ncex-ai) t h(ncex-nreg) t h(ncex-niord) t h(ncex- niowr ) ai14895b
electrical characteristics stm32f103xf, stm32f103xg 74/120 doc id 16554 rev 3 figure 31. pc card/compactflash controller waveforms for common memory write access t d(nce4_1-nwe) t w(nwe) t h(nwe-d) t v(nce4_1-a) t d(nreg-nce4_1) t d(niord-nce4_1) t h(nce4_1-ai) memxhiz =1 t v(nwe-d) t h(nce4_1-nreg) t h(nce4_1-niord) t h(nce4_1-niowr) ai14896b fsmc_nwe fsmc_n oe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nwe-nce4_1) t d(d-nwe) fsmc_nce4_2 high
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 75/120 figure 32. pc card/compactflash controller waveforms for attribute memory read access 1. only data bits 0...7 are read (bits 8...15 are disregarded). t d(nce4_1-noe) t w(noe) t su(d-noe) t h(noe-d) t v(nce4_1-a) t h(nce4_1-ai) t d(nreg-nce4_1) t h(nce4_1-nreg) ai14897b fsmc_nwe fsmc_noe fsmc_d[15:0] (1) fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(noe-nce4_1) high
electrical characteristics stm32f103xf, stm32f103xg 76/120 doc id 16554 rev 3 figure 33. pc card/compactflash controller waveforms for attribute memory write access 1. only data bits 0...7 are driven (bits 8...15 remains hiz). figure 34. pc card/compactflash controller waveforms for i/o space read access t w(nwe) t v(nce4_1-a) t d(nreg-nce4_1) t h(nce4_1-ai) t h(nce4_1-nreg) t v(nwe-d) ai14898b fsmc_nwe fsmc_noe fsmc_d[7:0](1) fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nwe-nce4_1) high t d(nce4_1-nwe) t d(niord-nce4_1) t w(niord) t su(d-niord) t d(niord-d) t v(ncex-a) t h(nce4_1-ai) ai14899b fsmc_nwe fsmc_noe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 77/120 figure 35. pc card/compactflash controller waveforms for i/o space write access t d.#%? .)/72 t w.)/72 t v.#%x ! t h.#%? !) t h.)/72 $ !44x(): t v.)/72 $ aib &3-#?.7% &3-#?./% &3-#?$;= &3-#?!;= &3-#?.#%? &3-#?.#%? &3-#?.2%' &3-#?.)/72 &3-#?.)/2$ table 40. switching characteristics for pc card/cf read and write cycles in attribute/common space symbol parameter min max unit t v(ncex-a) fsmc_ncex low to fsmc_ay valid - 0 ns t h(ncex-ai) fsmc_ncex high to fsmc_ax invalid 0 - t d(nreg-ncex) fsmc_ncex low to fsmc_nreg valid - 2 t h(ncex-nreg) fsmc_ncex high to fsmc_nreg invalid t hclk + 4 - t d(ncex_nwe) fsmc_ncex low to fsmc_nwe low - 5t hclk + 1 t d(ncex_noe) fsmc_ncex low to fsmc_noe low - 5t hclk + 1 t w(noe) fsmc_noe low width 8t hclk - 0.5 8t hclk + 1 t d(noe-ncex fsmc_noe high to fsmc_ncex high 5t hclk - 0.5 - t su(d-noe) fsmc_d[15:0] valid data before fsmc_noe high 32 - t h(noe-d) fsmc_noe high to fsmc_d[15:0] invalid t hclk - t w(nwe) fsmc_nwe low width 8t hclk ? 1 8t hclk + 4 t d(nwe_ncex) fsmc_nwe high to fsmc_ncex high 5t hclk + 1.5 - t d(ncex-nwe) fsmc_ncex low to fsmc_nwe low - 5t hclk + 1 t v(nwe-d) fsmc_nwe low to fsmc_d[15:0] valid - 0 t h(nwe-d) fsmc_nwe high to fsmc_d[15:0] invalid 11t hclk - t d(d-nwe) fsmc_d[15:0] valid before fsmc_nwe high 13t hclk + 2.5 -
electrical characteristics stm32f103xf, stm32f103xg 78/120 doc id 16554 rev 3 nand controller waveforms and timings figure 36 through figure 39 represent synchronous waveforms and ta bl e 43 provides the corresponding timings. the results shown in th is table are obtained with the following fsmc configuration: com.fsmc_setuptime = 0x00; com.fsmc_waitsetuptime = 0x02; com.fsmc_holdsetuptime = 0x01; com.fsmc_hizsetuptime = 0x00; att.fsmc_setuptime = 0x00; att.fsmc_waitsetuptime = 0x02; att.fsmc_holdsetuptime = 0x01; att.fsmc_hizsetuptime = 0x00; bank = fsmc_bank_nand; memorydatawidth = fsmc_memorydatawidth_16b; ecc = fsmc_ecc_enable; eccpagesize = fsmc_eccpagesize_512bytes; tclrsetuptime = 0; tarsetuptime = 0; table 41. switching characteristics for pc card/cf read and write cycles in i/o space symbol parameter min max unit tw (niowr) fsmc_niowr low width 8 thclk - ns tv (niowr-d) fsmc_niowr low to fsmc_d[15:0] valid - 5 thclk - 4 ns th (niowr-d) fsmc_niowr high to fsmc_d[15:0] invalid 11thclk - 7 -ns td (nce4_1-niowr) fsmc_nce4_1 low to fsmc_niowr valid - 5thclk + 1 ns th (ncex-niowr) fsmc_ncex high to fsmc_niowr invalid 5thclk - 2.5 -ns td (niord-ncex) fsmc_ncex low to fsmc_niord valid - 5thclk - 0.5 ns th (ncex-niord) fsmc_ncex high to fsmc_niord) valid 5 thclk - 0.5 -ns tw (niord) fsmc_niord low width 8thclk - ns tsu (d-niord) fsmc_d[15:0] valid before fsmc_niord high 28 ns td (niord-d) fsmc_d[15:0] valid after fsmc_niord high 3 ns
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 79/120 figure 36. nand controller waveforms for read access figure 37. nand controller waveforms for write access figure 38. nand controller waveforms for common memo ry read access fsmc_nwe fsmc_noe (nre) fsmc_d[15:0] t su(d-noe) t h(noe-d) ai14901b ale (fsmc_a17) cle (fsmc_a16) fsmc_ncex low t d(ale-noe) t h(noe-ale) t h(nwe-d) t v(nwe-d) ai14902b fsmc_nwe fsmc_noe (nre) fsmc_d[15:0] ale (fsmc_a17) cle (fsmc_a16) fsmc_ncex low t d(ale-nwe) t h(nwe-ale) fsmc_nwe fsmc_n oe fsmc_d[15:0] t w(noe) t su(d-noe) t h(noe-d) ai14912b ale (fsmc_a17) cle (fsmc_a16) fsmc_ncex low t d(ale-noe) t h(noe-ale)
electrical characteristics stm32f103xf, stm32f103xg 80/120 doc id 16554 rev 3 figure 39. nand controller waveforms for common memory write access table 42. switching characteristics for nand flash read cycles (1) 1. c l = 15 pf. symbol parameter min max unit t w(noe) fsmc_noe low width 3t hclk ? 1 3t hclk + 1 ns t su(d-noe) fsmc_d[15:0] valid data before fsmc_noe high 13 - ns t h(noe-d) fsmc_d[15:0] valid data after fsmc_noe high 0 - ns t d(ale-noe) fsmc_ale valid before fsmc_noe low - 2t hclk ns t h(noe-ale) fsmc_nwe high to fsmc_ale invalid 2t hclk - ns table 43. switching characterist ics for nand flash write cycles (1) 1. c l = 15 pf. symbol parameter min max unit t w(nwe) fsmc_nwe low width 3t hclk 3t hclk ns t v(nwe-d) fsmc_nwe low to fsmc_d[15:0] valid - 0 ns t h(nwe-d) fsmc_nwe high to fsmc_d[15:0] invalid 2t hclk + 2 - ns t d(ale-nwe) fsmc_ale valid before fsmc_nwe low - 3t hclk + 1.5 ns t h(nwe-ale) fsmc_nwe high to fsmc_ale invalid 3t hclk + 8 - ns t d(ale-noe) fsmc_ale valid before fsmc_noe low - 2t hclk ns t h(noe-ale) fsmc_nwe high to fsmc_ale invalid 2t hclk - ns t w(nwe) t h(nwe-d) t v(nwe-d) ai14913b fsmc_nwe fsmc_n oe fsmc_d[15:0] t d(d-nwe) ale (fsmc_a17) cle (fsmc_a16) fsmc_ncex low t d(ale-noe) t h(noe-ale)
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 81/120 5.3.11 emc characteristics susceptibility tests ar e performed on a sample basis during device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in ta b l e 44 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) table 44. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp144, t a = +25 c, f hclk = 72 mhz conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp144, t a = +25 c, f hclk = 72 mhz conforms to iec 61000-4-4 4a
electrical characteristics stm32f103xf, stm32f103xg 82/120 doc id 16554 rev 3 prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be appflied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o ports). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 5.3.12 absolute maximum rati ngs (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determine its perfor mance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. table 45. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/48 mhz 8/72 mhz s emi peak level v dd = 3.3 v, t a = 25 c, lqfp144 package compliant with iec 61967-2 0.1 to 30 mhz 8 12 dbv 30 to 130 mhz 31 21 130 mhz to 1ghz 28 33 sae emi level 4 4 - table 46. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c, conforming to jesd22-a114 22000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c, conforming to jesd22-c101 ii 500
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 83/120 static latch-up two complementary static tests are required on six parts to assess the latch-up performance: a supply overvoltage is applied to each power supply pin a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. 5.3.13 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection a ccidentally happens, susceptibilit y tests are performed on a sample basis during device characterization. functional susceptibilty to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode. while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (>5 lsb tue), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). the test results are given in ta b l e 48 table 47. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a table 48. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on osc_in32, osc_out32, pa4, pa5, pc13 -0 +0 ma injected current on all ft pins -5 +0 injected current on any other pin -5 +5
electrical characteristics stm32f103xf, stm32f103xg 84/120 doc id 16554 rev 3 5.3.14 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in ta bl e 49 are derived from tests performed under the conditions summarized in ta b l e 10 . all i/os are cmos and ttl compliant. all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 40 and figure 41 for standard i/os, and in figure 42 and figure 43 for 5 v tolerant i/os. table 49. i/o static characteristics symbol parameter conditions min typ max unit v il standard io input low level voltage ?0.3 - 0.28*(v dd -2 v)+0.8 v v io ft (1) input low level voltage ?0.3 - 0.32*(v dd -2 v)+0.75 v v v ih standard io input high level voltage 0.41*(v dd -2 v)+1.3 v -v dd +0.3 v io ft (1) input high level voltage v dd > 2 v 0.42*(v dd -2 v)+1 v - 5.5 v v dd 2 v 5.2 v hys standard io schmitt trigger voltage hysteresis (2) 200 - - mv io ft schmitt trigger voltage hysteresis (2) 5% v dd (3) - -mv i lkg input leakage current (4) v ss v in v dd standard i/os -- 1 a v in = 5 v, i/o ft - - 3 r pu weak pull-up equivalent resistor (5) v in = v ss 30 40 50 k r pd weak pull-down equivalent resistor (5) v in = v dd 30 40 50 k c io i/o pin capacitance - 5 - pf 1. ft = five-volt tolerant. in order to sustain a voltage higher than v dd +0.3 the internal pull-up/pull-down resistors must be disabled. 2. hysteresis voltage between schmitt trigger switching levels. based on characteriza tion, not tested in production. 3. with a minimum of 100 mv. 4. leakage could be higher than max. if negativ e current is injected on adjacent pins. 5. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this mos/nmos contribution to the series resistance is minimum (~10% order) .
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 85/120 figure 40. standard i/o input characteristics - cmos port figure 41. standard i/o input characteristics - ttl port aib 6 $$ 6 )nputrange notguaranteed 6 )( 6 $$ #-/3standardrequirement6 )( 6 $$ 6 )( 6 ), 6 #-/3standardrequirement6 ), 6 $$ 6 ), 6 ## 7 ),max 7 )(min ai )nputrange notguaranteed 6 )( 6 ), 6 44,requirements 6 )( 6 6 )( 6 $$ 6 ), 6 $$ 44,requirements 6 ), 6 6 $$ 6 7 ),max 7 )(min
electrical characteristics stm32f103xf, stm32f103xg 86/120 doc id 16554 rev 3 figure 42. 5 v tolerant i/o input characteristics - cmos port figure 43. 5 v tolerant i/o input characteristics - ttl port output driving current the gpios (general purpose input/outputs) can sink or source up to 8 ma, and sink or source up to 20 ma (with a relaxedv ol/ v oh ) except pc13, pc14 and pc15 which can sink or source up to 3 ma. when using the gpios pc13 to pc15 in output mode, the speed should not exceed 2 mhz with a maximum load of 30 pf. in the user application, the number of i/o pins which can drive current must be limited to respect the absolute maxi mum rating specified in section 5.2 : the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see ta bl e 8 ). the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see ta b l e 8 ). 6$$ #-/3standardrequirements6 )( 6 $$ #-/3standardrequirment6 ), 6 $$ 6 )( 6 ), 6 6 $$ 6 )nputrange notguaranteed aib 6 )( 6 $$ 6 ), 6 $$ notguaranteed )nputrange 44,requirement6 )( 6 6 )(
6 $$ 6 ),
6 $$ 44,requirements6 ), 6 6 )( 6 ), 6 6 $$ 6 7 ),max 7 )(min ai
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 87/120 output voltage levels unless otherwise specified, the parameters given in ta bl e 50 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 10 . all i/os are cmos and ttl compliant. table 50. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always re spect the absolute maximu m rating specified in table 8 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin when 8 pins are sunk at same time ttl port (3) i io = +8 ma 2.7 v < v dd < 3.6 v -0.4 v v oh (2) 2. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 8 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?0.4 - v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at same time cmos port (3) i io =+ 8ma 2.7 v < v dd < 3.6 v 3. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. -0.4 v v oh (2) output high level voltage for an i/o pin when 8 pins are sourced at same time 2.4 - v ol (1)(4) 4. based on characterization data, not tested in production. output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +20 ma 2.7 v < v dd < 3.6 v -1.3 v v oh (2)(4) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?1.3 - v ol (1)(4) output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +6 ma 2 v < v dd < 2.7 v -0.4 v v oh (2)(4) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?0.4 -
electrical characteristics stm32f103xf, stm32f103xg 88/120 doc id 16554 rev 3 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 44 and ta bl e 51 , respectively. unless otherwise specified, the parameters given in ta bl e 51 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 10 . table 51. i/o ac characteristics (1) 1. the i/o speed is configured using the modex[1:0] bi ts. refer to the stm32f10xxx reference manual for a description of gpio port configuration register. modex[1:0] bit value (1) symbol parameter conditions min max unit 10 f max(io)out maximum frequency (2) 2. the maximum frequency is defined in figure 44 . c l = 50 pf, v dd = 2 v to 3.6 v - 2 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v -125 (3) 3. guaranteed by design, not tested in production. ns t r(io)out output low to high level rise time -125 (3) 01 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v - 10 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v -25 (3) ns t r(io)out output low to high level rise time -25 (3) 11 f max(io)out maximum frequency (2) c l = 30 pf, v dd = 2.7 v to 3.6 v - 50 mhz c l = 50 pf, v dd = 2.7 v to 3.6 v - 30 mhz c l = 50 pf, v dd = 2 v to 2.7 v - 20 mhz t f(io)out output high to low level fall time c l = 30 pf, v dd = 2.7 v to 3.6 v - 5 (3) ns c l = 50 pf, v dd = 2.7 v to 3.6 v - 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v - 12 (3) t r(io)out output low to high level rise time c l = 30 pf, v dd = 2.7 v to 3.6 v - 5 (3) c l = 50 pf, v dd = 2.7 v to 3.6 v - 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v - 12 (3) -t extipw pulse width of external signals detected by the exti controller 10 - ns
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 89/120 figure 44. i/o ac characteristics definition 5.3.15 nrst pin characteristics the nrst pin input driver uses cmos techno logy. it is connected to a permanent pull-up resistor, r pu (see ta bl e 49 ). unless otherwise specified, the parameters given in ta bl e 52 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 10 . figure 45. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 52 . otherwise the reset will not be taken into account by the device. ai14131 10% 90% 50% t r(io)out output ext ernal on 50pf maximum frequency is achieved if (t r + t f ) 2/3)t and if the duty cycle is (45-55%) 10 % 50% 90% when loaded by 50pf t t r(io)out table 52. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) 1. guaranteed by design, not tested in production. nrst input low level voltage ?0.5 - 0.8 v v ih(nrst) (1) nrst input high level voltage 2 - v dd +0.5 v hys(nrst) nrst schmitt trigger voltage hysteresis - 200 - mv r pu weak pull-up equivalent resistor (2) 2. the pull-up is designed with a true resistance in seri es with a switchable pmos . this pmos contribution to the series resistance must be minimum (~10% order) . v in = v ss 30 40 50 k v f(nrst) (1) nrst input filtered pulse - - 100 ns v nf(nrst) (1) nrst input not filtered pulse 300 - - ns a i141 3 2d s tm 3 2f10xxx r pu nr s t (2) v dd filter intern a l re s et 0.1 f extern a l re s et circ u it (1)
electrical characteristics stm32f103xf, stm32f103xg 90/120 doc id 16554 rev 3 5.3.16 tim time r characteristics the parameters given in ta bl e 53 are guaranteed by design. refer to section 5.3.14: i/o port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output). table 53. timx (1) characteristics 1. timx is used as a general term to refer to the tim1, tim2, tim3 and tim4 timers. symbol parameter conditions min max unit t res(tim) timer resolution time 1- t timxclk f timxclk = 72 mhz 13.9 - ns f ext timer external clock frequency on ch1 to ch4 0 f timxclk /2 mhz f timxclk = 72 mhz 0 36 mhz res tim timer resolution - 16 bit t counter 16-bit counter clock period when internal clock is selected 1 65536 t timxclk f timxclk = 72 mhz 0.0139 910 s t max_count maximum possible count - 65536 65536 t timxclk f timxclk = 72 mhz - 59.6 s
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 91/120 5.3.17 communications interfaces i 2 c interface characteristics unless otherwise specified, the parameters given in ta bl e 54 are derived from tests performed under ambient temperature, f pclk1 frequency and v dd supply voltage conditions summarized in ta b l e 10 . the stm32f103xc, stm32f103xd and stm32f103xestm32f103xf and stm32f103xg performance line i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: the i/o pins sda and scl are mapped to are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in ta b l e 54 . refer also to section 5.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl) . table 54. i 2 c characteristics symbol parameter standard mode i 2 c (1) 1. guaranteed by design, not tested in production. fast mode i 2 c (1) (2) 2. f pclk1 must be at least 2 mhz to achieve standard mode i 2 c frequencies. it must be at least 4 mhz to achieve the fast mode i 2 c frequencies and it must be a multiple of 10 mhz in order to reach the i2c fast mode maximum clock speed of 400 khz. unit min max min max t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time 0 (3) 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. -0 (4) 4. the device must internally provide a hold time of at least 300ns for th e sda signal in order to bridge the undefined region of the falling edge of scl. 900 (3) t r(sda) t r(scl) sda and scl rise time - 1000 20 + 0.1c b 300 t f(sda) t f(scl) sda and scl fall time - 300 - 300 t h(sta) start condition hold time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - s t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - s c b capacitive load for each bus line - 400 - 400 pf
electrical characteristics stm32f103xf, stm32f103xg 92/120 doc id 16554 rev 3 figure 46. i 2 c bus ac waveforms and measurement circuit 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14149c start sd a 100 4.7k i 2 c bus 4.7k 100 v dd v dd stm32f103xx sda scl t f(sda) t r(sda) scl t h(sta) t w(sclh) t w(scll) t su(sda) t r(scl) t f(scl) t h(sda) s tart repeated start t su(sta) t su(sto) s top t w(sto:sta) table 55. scl frequency (f pclk1 = 36 mhz.,v dd = 3.3 v) (1)(2) 1. r p = external pull-up resistance, f scl = i 2 c speed. 2. for speeds around 200 khz, the tole rance on the achieved speed is of 5%. for other speed ranges, the tolerance on the achieved speed 2%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) i2c_ccr value r p = 4.7 k 400 0x801e 300 0x8028 200 0x803c 100 0x00b4 50 0x0168 20 0x0384
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 93/120 i 2 s - spi characteristics unless otherwise specified, the parameters given in ta bl e 56 for spi or in ta bl e 57 for i 2 s are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in ta bl e 10 . refer to section 5.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi and ws, ck, sd for i 2 s). table 56. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode - 18 mhz slave mode - 18 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf - 8 ns ducy(sck) spi slave input clock duty cycle slave mode 30 70 % t su(nss) (1) 1. based on characterization , not tested in production. nss setup time slave mode 4t pclk - ns t h(nss) (1) nss hold time slave mode 2t pclk - t w(sckh) (1) t w(sckl) (1) sck high and low time master mode, f pclk = 36 mhz, presc = 4 50 60 t su(mi) (1) t su(si) (1) data input setup time master mode 5 - slave mode 5 - t h(mi) (1) data input hold time master mode 5 - t h(si) (1) slave mode 4 - t a(so) (1)(2) 2. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. data output access time slave mode, f pclk = 20 mhz 0 3t pclk t dis(so) (1)(3) 3. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z data output disable time slave mode 2 10 t v(so) (1) data output valid time slave mode (after enable edge) - 25 t v(mo) (1) data output valid time master mode (after enable edge) - 5 t h(so) (1) data output hold time slave mode (after enable edge) 15 - t h(mo) (1) master mode (after enable edge) 2 -
electrical characteristics stm32f103xf, stm32f103xg 94/120 doc id 16554 rev 3 figure 47. spi timing diagram - slave mode and cpha = 0 figure 48. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14134c sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 95/120 figure 49. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14136 sck input cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo)
electrical characteristics stm32f103xf, stm32f103xg 96/120 doc id 16554 rev 3 table 57. i 2 s characteristics symbol parameter conditions min max unit ducy(sck) i2s slave input clock duty cycle slave mode 30 70 % f ck 1/t c(ck) i 2 s clock frequency master mode (data: 16 bits, audio frequency = 48 khz) 1.522 1.525 mhz slave mode 0 6.5 t r(ck) t f(ck) i 2 s clock rise and fall time capacitive load c l = 50 pf - 8 ns t v(ws) (1) ws valid time master mode 3 - t h(ws) (1) ws hold time master mode i2s2 2 - i2s3 0 - t su(ws) (1) ws setup time slave mode 4 - t h(ws) (1) ws hold time slave mode 0 - t w(ckh) (1) ck high and low time master f pclk = 16 mhz, audio frequency = 48 khz 312.5 - t w(ckl) (1) 345 - t su(sd_mr) (1) data input setup time master receiver i2s2 2 - i2s3 6.5 - t su(sd_sr) (1) data input setup time slave receiver 1.5 - t h(sd_mr) (1)(2) data input hold time master receiver 0 - t h(sd_sr) (1)(2) slave receiver 0.5 - t v(sd_st) (1)(2) data output valid time slave transmitter (after enable edge) - 18 t h(sd_st) (1) data output hold time slave transmitter (after enable edge) 11 - t v(sd_mt) (1)(2) data output valid time master transmitter (after enable edge) - 3 t h(sd_mt) (1) data output hold time master transmitter (after enable edge) 0- 1. based on design simulation and/or characte rization results, not tested in production. 2. depends on f pclk . for example, if f pclk =8 mhz, then t pclk = 1/f plclk =125 ns.
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 97/120 figure 50. i 2 s slave timing diagram (philips protocol) (1) 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. figure 51. i 2 s master timing diagram (philips protocol) (1) 1. based on characterization , not tested in production. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. ck inp u t cpol = 0 cpol = 1 t c(ck) w s inp u t s d tr a n s mit s d receive t w(ckh) t w(ckl) t su (w s ) t v( s d_ s t) t h( s d_ s t) t h(w s ) t su ( s d_ s r) t h( s d_ s r) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14 88 1 b l s b receive (2) l s b tr a n s mit (2) ck o u tp u t cpol = 0 cpol = 1 t c(ck) w s o u tp u t s d receive s d tr a n s mit t w(ckh) t w(ckl) t su ( s d_mr) t v( s d_mt) t h( s d_mt) t h(w s ) t h( s d_mr) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14 88 4 b t f(ck) t r(ck) t v(w s ) l s b receive (2) l s b tr a n s mit (2)
electrical characteristics stm32f103xf, stm32f103xg 98/120 doc id 16554 rev 3 sd/sdio mmc card host interface (sdio) characteristics unless otherwise specified, the parameters given in ta bl e 58 are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in ta b l e 10 . refer to section 5.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (d[7:0], cmd, ck). figure 52. sdio high-speed mode figure 53. sd default mode t w(ckh) ck d, cmd (output) d, cmd (input) t c t w(ckl) t ov t oh t isu t ih t f t r ai14887 ck d, cmd (output) t ovd t ohd ai14888
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 99/120 usb characteristics the usb interface is usb-if certified (full speed). table 58. sd / mmc characteristics symbol parameter conditions min max unit f pp clock frequency in data transfer mode c l 30 pf 0 48 mhz t w(ckl) clock low time, f pp = 16 mhz c l 30 pf 32 - ns t w(ckh) clock high time, f pp = 16 mhz c l 30 pf 30 - t r clock rise time c l 30 pf - 4 t f clock fall time c l 30 pf - 5 cmd, d inputs (referenced to ck) t isu input setup time c l 30 pf 2 - ns t ih input hold time c l 30 pf 0 - cmd, d outputs (referenced to ck) in mmc and sd hs mode t ov output valid time c l 30 pf - 6 ns t oh output hold time c l 30 pf 0 - cmd, d outputs (referenced to ck) in sd default mode (1) 1. refer to sdio_clkcr, the sdi clock control register to control the ck output. t ovd output valid default time c l 30 pf - 7 ns t ohd output hold default time c l 30 pf 0.5 - table 59. usb startup time symbol parameter max unit t startup (1) 1. guaranteed by design, not tested in production. usb transceiver startup time 1 s
electrical characteristics stm32f103xf, stm32f103xg 100/120 doc id 16554 rev 3 figure 54. usb timings: definition of data signal rise and fall time 5.3.18 can (controller area network) interface refer to section 5.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (can_tx and can_rx). table 60. usb dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input levels v dd usb operating voltage (2) 2. to be compliant with the usb 2.0 fu ll-speed electrical specification, the usbdp (d+) pin should be pulled up with a 1.5 k resistor to a 3.0-to-3.6 v voltage range. 3.0 (3) 3. the stm32f103xx usb functionality is ensured dow n to 2.7 v but not the full usb electrical characteristics which are degr aded in the 2.7-to-3.0 v v dd voltage range. 3.6 v v di (4) 4. guaranteed by characterizati on, not tested in production. differential input sensitivity i(usbdp, usbdm) 0.2 v v cm (4) differential common mode range includes v di range 0.8 2.5 v se (4) single ended receiver threshold 1.3 2.0 output levels v ol static output level low r l of 1.5 k to 3.6 v (5) 5. r l is the load connected on the usb drivers 0.3 v v oh static output level high r l of 15 k to v ss (5) 2.8 3.6 table 61. usb: full-speed electrical characteristics driver characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter conditions min max unit t r rise time (2) 2. measured from 10% to 90% of the data signal. for more detailed informations, please refer to usb specification - chapt er 7 (version 2.0). c l = 50 pf 420ns t f fall time (2) c l = 50 pf 4 20 ns t rfm rise/ fall time matching t r /t f 90 110 % v crs output signal crossover voltage 1.3 2.0 v ai14137 t f differen tial data lines v ss v cr s t r crossover points
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 101/120 5.3.19 12-bit adc characteristics unless otherwise specified, the parameters given in ta bl e 62 are preliminary values derived from tests performed under ambient temperature, f pclk2 frequency and v dda supply voltage conditions summarized in ta bl e 10 . note: it is recommended to perform a calibration after each power-up. table 62. adc characteristics symbol parameter conditions min typ max unit v dda power supply 2.4 - 3.6 v v ref+ positive reference voltage 2.4 - v dda v i vref current on the v ref input pin -160220 (1) a f adc adc clock frequency 0.6 - 14 mhz f s (2) sampling rate 0.05 - 1 mhz f trig (2) external trigger frequency f adc = 14 mhz - - 823 khz --171/f adc v ain conversion voltage range (3) 0 (v ssa or v ref- tied to ground) -v ref+ v r ain (2) external input impedance see equation 1 and table 63 for details --50k r adc (2) sampling switch resistance - - 1 k c adc (2) internal sample and hold capacitor --8pf t cal (2) calibration time f adc = 14 mhz 5.9 s 83 1/f adc t lat (2) injection trigger conversion latency f adc = 14 mhz - - 0.214 s --3 (4) 1/f adc t latr (2) regular trigger conversion latency f adc = 14 mhz - - 0.143 s --2 (4) 1/f adc t s (2) sampling time f adc = 14 mhz 0.107 - 17.1 s 1.5 - 239.5 1/f adc t stab (2) power-up time 0 0 1 s t conv (2) total conversion time (including sampling time) f adc = 14 mhz 1 18 s 14 to 252 (t s for sampling +12.5 for successive approximation) 1/f adc 1. based on characterization, not tested in production. 2. guaranteed by design, not tested in production. 3. v ref+ can be internally connected to v dda and v ref- can be internally connected to v ssa , depending on the package. refer to section 3: pinouts and pin descriptions for further details. 4. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 62 .
electrical characteristics stm32f103xf, stm32f103xg 102/120 doc id 16554 rev 3 equation 1: r ain max formula the formula above ( equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). table 63. r ain max for f adc = 14 mhz (1) 1. guaranteed by design, not tested in production. t s (cycles) t s (s) r ain max (k ) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 na 239.5 17.1 na table 64. adc accuracy - limited test conditions (1)(2) 1. adc dc accuracy values are m easured after internal calibration. 2. adc accuracy vs. negative injection current: in jecting negative current on any of the standard (non- robust) analog input pins should be av oided as this significantly reduce s the accuracy of the conversion being performed on another analog input. it is recommend ed to add a schottky diode (pin to ground) to standard analog pins which may pot entially inject negative current. any positive injection current with in the limits specified for i inj(pin) and i inj(pin) in section 5.3.14 does not affect the adc accuracy. symbol parameter test conditions typ max (3) 3. based on characterisation , not tested in production. unit et total unadjusted error f pclk2 = 56 mhz, f adc = 14 mhz, r ain < 10 k , v dda = 3 v to 3.6 v t a = 25 c measurements made after adc calibration v ref+ = v dda 1.3 2 lsb eo offset error 1 1.5 eg gain error 0.5 1.5 ed differential linearity error 0.7 1 el integral linearity error 0.8 1.5 r ain t s f adc c adc 2 n2 + () ln --------------------------------------------------------------- - r adc ? <
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 103/120 figure 55. adc accuracy characteristics table 65. adc accuracy (1) (2)(3) 1. adc dc accuracy values are m easured after internal calibration. 2. better performance could be achieved in restricted v dd , frequency, v ref and temperature ranges. 3. adc accuracy vs. negative injection current: in jecting negative current on any of the standard (non- robust) analog input pins should be av oided as this significantly reduce s the accuracy of the conversion being performed on another analog input. it is recommend ed to add a schottky diode (pin to ground) to standard analog pins which may pot entially inject negative current. any positive injection current with in the limits specified for i inj(pin) and i inj(pin) in section 5.3.14 does not affect the adc accuracy. symbol parameter test conditions typ max (4) 4. preliminary values. unit et total unadjusted error f pclk2 = 56 mhz, f adc = 14 mhz, r ain < 10 k , v dda = 2.4 v to 3.6 v measurements made after adc calibration 2 5 lsb eo offset error 1.5 2.5 eg gain error 1.5 3 ed differential linearity error 1 2 el integral linearity error 1.5 3 e o e g 1lsb ideal (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. 4095 4094 4093 5 4 3 2 1 0 7 6 1234567 4093 4094 4095 4096 (1) (2) e t e d e l (3) v dda v ssa ai14395b v ref+ 4096 (or depending on package)] v dda 4096 [1lsb ideal =
electrical characteristics stm32f103xf, stm32f103xg 104/120 doc id 16554 rev 3 figure 56. typical connection diagram using the adc 1. refer to table 62 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 57 or figure 58 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed them as close as possible to the chip. figure 57. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ and v ref? inputs are available only on 100-pin packages. ai14150c stm32f103xx v dd ainx i l 1 a 0.6 v v t r ain (1) c parasitic v ain 0.6 v v t r adc (1) 12-bit converter c adc (1) sample and hold adc converter v ref+ (see note 1) stm32f103xx v dda v ssa /v ref? (see note 1) 1 f // 10 nf 1 f // 10 nf ai14388b
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 105/120 figure 58. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ and v ref? inputs are available only on 100-pin packages. v ref+ /v dda stm32f103xx 1 f // 10 nf v ref? /v ssa ai14389 (see note 1) (see note 1)
electrical characteristics stm32f103xf, stm32f103xg 106/120 doc id 16554 rev 3 5.3.20 dac elect rical specifications table 66. dac characteristics symbol parameter min typ max unit comments v dda analog supply voltage 2.4 - 3.6 v v ref+ reference supply voltage 2.4 - 3.6 v v ref+ must always be below v dda v ssa ground 0 - 0 v r load (1) resistive load vs. v ssa with buffer on 5- - k resistive load vs. v dda with buffer on 15 - - k r o (1) impedance output with buffer off -- 15 k when the buffer is off, the minimum resistive load between dac_out and v ss to have a 1% accuracy is 1.5 m c load (1) capacitive load - - 50 pf maximum capacitive load at dac_out pin (when the buffer is on). dac_out min (1) lower dac_out voltage with buffer on 0.2 - - v it gives the maximum output excursion of the dac. it corresponds to 12-bit input code (0x0e0) to (0xf1c) at v ref+ = 3.6 v and (0x155) and (0xeab) at v ref+ = 2.4 v dac_out max (1) higher dac_out voltage with buffer on --v dda ? 0.2 v dac_out min (1) lower dac_out voltage with buffer off -0.5 mv it gives the maximum output excursion of the dac. dac_out max (1) higher dac_out voltage with buffer off - v ref+ ? 10 mv v i ddvref+ dac dc current consumption in quiescent mode (standby mode) - 380 a with no load, worst code (0x0e4) at v ref+ = 3.6 v in terms of dc consumption on the inputs i dda dac dc current consumption in quiescent mode (standby mode) - 380 a with no load, middle code (0x800) on the inputs - 480 a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs dnl (2) differential non linearity difference between two consecutive code-1lsb) - 0.5 lsb given for the dac in 10-bit configuration -3 lsb given for the dac in 12-bit configuration
stm32f103xf, stm32f103xg electrical characteristics doc id 16554 rev 3 107/120 figure 59. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to r educe the output impedance and to dr ive external loads directly without the use of an external operational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. inl (2) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023) -- 1lsb given for the dac in 10-bit configuration -- 4lsb given for the dac in 12-bit configuration offset (2) offset error (difference between measured value at code (0x800) and the ideal value = v ref+ /2) -- 10mv given for the dac in 12-bit configuration -- 3lsb given for the dac in 10-bit at v ref+ = 3.6 v -- 12lsb given for the dac in 12-bit at v ref+ = 3.6 v gain error (2) gain error - - 0.5 % given for the dac in 12bit configuration t settling (2) settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when dac_out reaches final value 1lsb -3 4 sc load 50 pf, r load 5 k update rate (2) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) -- 1ms/sc load 50 pf, r load 5 k t wakeup (2) wakeup time from off state (setting the enx bit in the dac control register) - 6.5 10 s c load 50 pf, r load 5 k input code between lowest and highest possible ones. psrr+ (1) power supply rejection ratio (to v dda ) (static dc measurement - ?67 ?40 db no r load , c load = 50 pf 1. guaranteed by design, not tested in production. 2. preliminary values. table 66. dac characteristics (continued) symbol parameter min typ max unit comments r load c load b u ffered/non- bu ffered dac dacx_out b u ffer(1) 12- b it digit a l to a n a log converter a i17157
electrical characteristics stm32f103xf, stm32f103xg 108/120 doc id 16554 rev 3 5.3.21 temperature sen sor characteristics table 67. ts characteristics symbol parameter min typ max unit t l (1) 1. based on characterization , not tested in production. v sense linearity with temperature - 1 2c avg_slope (1) average slope 4.0 4.3 4.6 mv/c v 25 (1) voltage at 25 c 1.34 1.43 1.52 v t start (2) 2. guaranteed by design, not tested in production. startup time 4 - 10 s t s_temp (3)(2) 3. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature --17.1s
stm32f103xf, stm32f103xg package characteristics doc id 16554 rev 3 109/120 6 package characteristics 6.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 60. recommended pcb design rules (0.80/0.75 mm pitch bga dpad dsm dpad 0.37 mm dsm 0.52 mm typ. (depends on solder mask registration tolerance ? non solder mask defined pads are recommended ? 4 to 6 mils screen print solder paste 0.37 mm aperture diameter ai15469
package characteristics stm32f103xf, stm32f103xg 110/120 doc id 16554 rev 3 figure 61. lfbga144 ? 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline 1. drawing is not to scale. table 68. lfbga144 ? 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max typ min max a1.700.0669 a1 0.21 0.0083 a2 1.07 0.0421 a3 0.27 0.0106 a4 0.85 0.0335 b 0.35 0.40 0.45 0.0138 0.0157 0.0177 d 9.85 10.00 10.15 0. 3878 0.3937 0.3996 d1 8.80 0.3465 e 9.85 10.00 10.15 0. 3878 0.3937 0.3996 e1 8.80 0.3465 e0.80 0.0315 f0.60 0.0236 ddd 0.10 0.0039 eee 0.15 0.0059 fff 0.08 0.0031 s e a ting pl a ne c a2 a4 a 3 c ddd a1 a b a d1 e f d f e1 e e m eee m cab c fff (144 ba ll s ) ? b m ? ? x 3 _me b a ll a1
stm32f103xf, stm32f103xg package characteristics doc id 16554 rev 3 111/120 figure 62. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline (1) figure 63. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. d1 d3 d e1 e3 e e pin 1 identification 73 72 37 36 109 144 108 1 aa2a1 b c a1 l l1 k seating plane c ccc c 0.25 mm gage plane me_1a 0.5 0.35 19.9 17.85 22.6 1.35 22.6 19.9 ai149 1 36 37 72 73 108 109 144 table 69. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a1.600.063 a1 0.05 0.15 0.002 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 21.80 22.00 22.20 0.8583 0.8661 0.874 d1 19.80 20.00 20.20 0.7795 0.7874 0.7953 d3 17.50 0.689 e 21.80 22.00 22.20 0.8583 0.8661 0.874 e1 19.80 20.00 20.20 0.7795 0.7874 0.7953 e3 17.50 0.689 e 0.50 0.0197 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 k 03.57 03.57 ccc 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f103xf, stm32f103xg 112/120 doc id 16554 rev 3 figure 64. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline (1) figure 65. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. d d1 d3 75 51 50 76 100 26 125 e3 e1 e e b pin 1 identification seating plane gage plane c a a2 a1 c ccc 0.25 mm 0.10 inch l l1 k c 1l_me 75 51 50 76 0.5 0. 3 16.7 14. 3 100 26 12. 3 25 1.2 16.7 1 a i14906 b table 70. lqpf100 ? 14 x 14 mm 100-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 15.80 16.00 16.20 0.622 0.6299 0.6378 d1 13.80 14.00 14.20 0.5433 0.5512 0.5591 d3 12.00 0.4724 e 15.80 16.00 16.20 0.622 0.6299 0.6378 e1 13.80 14.00 14.20 0.5433 0.5512 0.5591 e3 12.00 0.4724 e 0.50 0.0197 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 k 03.57 03.57 ccc 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
stm32f103xf, stm32f103xg package characteristics doc id 16554 rev 3 113/120 figure 66. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline (1) figure 67. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. 5w_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 32 33 48 49 b 64 1 pin 1 identification 16 17 48 32 49 64 17 116 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909 table 71. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 11.800 12.000 12.200 0.4646 0.4724 0.4803 d1 9.800 10.000 10.200 0.3858 0.3937 0.4016 d. 7.500 e 11.800 12.000 12.200 0.4646 0.4724 0.4803 e1 9.800 10.00 10.200 0.3858 0.3937 0.4016 e 0.500 0.0197 k 03.57 03.57 l 0.450 0.600 0.75 0.0177 0.0236 0.0295 l1 1.000 0.0394 ccc 0.080 0.0031 n number of pins 64 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f103xf, stm32f103xg 114/120 doc id 16554 rev 3 6.2 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in ta bl e 10: general operating conditions on page 41 . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: t a max is the maximum ambient temperature in c, ja is the package junction-to-ambient thermal resistance, in c/w, p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 6.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). ava ilable from www.jedec.org table 72. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lfbga144 - 10 10 mm / 0.8 mm pitch 40 c/w thermal resistance junction-ambient lqfp144 - 20 20 mm / 0.5 mm pitch 30 thermal resistance junction-ambient lqfp100 - 14 14 mm / 0.5 mm pitch 46 thermal resistance junction-ambient lqfp64 - 10 10 mm / 0.5 mm pitch 45
stm32f103xf, stm32f103xg package characteristics doc id 16554 rev 3 115/120 6.2.2 selecting the pro duct temperature range when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in ta b l e 73: stm32f103xf and stm32f103xg ordering information scheme . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. as applications do not commonly use the stm32f103xf and stm32f103xg at maximum dissipation, it is useful to calculate the exac t power consumption and junction temperature to determine which temperature range will be best suited to the application. the following examples show how to calculate the temperature range needed for a given application. example 1: high-performance application assuming the following application conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 8 i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 20 8 ma 0.4 v + 8 20 ma 1.3 v = 272 mw this gives: p intmax = 175 mw and p iomax = 272 mw: p dmax = 175 + 272 = 447 mw thus: p dmax = 447 mw using the values obtained in ta b l e 72 t jmax is calculated as follows: ? for lqfp100, 46 c/w t jmax = 82 c + (46 c/w 447 mw) = 82 c + 20.6 c = 102.6 c this is within the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at least with the temperature range suffix 6 (see ta bl e 73: stm32f103xf and stm32f103xg ordering information scheme ). example 2: high-temperature application using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature t j remains within the specified range. assuming the following application conditions: maximum ambient temperature t amax = 115 c (measured according to jesd51-2), i ddmax = 20 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 20 ma 3.5 v= 70 mw p iomax = 20 8 ma 0.4 v = 64 mw this gives: p intmax = 70 mw and p iomax = 64 mw: p dmax = 70 + 64 = 134 mw thus: p dmax = 134 mw
package characteristics stm32f103xf, stm32f103xg 116/120 doc id 16554 rev 3 using the values obtained in ta b l e 72 t jmax is calculated as follows: ? for lqfp100, 46 c/w t jmax = 115 c + (46 c/w 134 mw) = 115 c + 6.2 c = 121.2 c this is within the range of the suffix 7 version parts (?40 < t j < 125 c). in this case, parts must be ordered at least with the temperature range suffix 7 (see ta bl e 73: stm32f103xf and stm32f103xg ordering information scheme ). figure 68. lqfp100 p d max vs. t a 0 100 200 300 400 500 600 700 65 75 85 95 105 115 125 135 t a (c) p d (mw) suffix 6 suffix 7
stm32f103xf, stm32f103xg part numbering doc id 16554 rev 3 117/120 7 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 73. stm32f103xf and stm32f103xg ordering information scheme example: stm32 f103 rf t 6 xxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 103 = performance line pin count r = 64 pins v = 100 pins z = 144 pins flash memory size f = 768 kbytes of flash memory g = 1 mbyte of flash memory package h = bga t = lqfp temperature range 6 = industrial temperature range, ?40 to 85 c. 7 = industrial temperature range, ?40 to 105 c. options xxx = programmed parts tr = tape and real
revision history stm32f103xf, stm32f103xg 118/120 doc id 16554 rev 3 8 revision history table 74. document revision history date revision changes 27-oct-2009 1 initial release. 15-nov-2010 2 lqfp64 package mechanical data updated: see figure 66: lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline and ta b l e 7 1 : lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data . internal code removed from table 73: stm32f103xf and stm32f103xg ordering information scheme . updated note 2 below table 54: i 2 c characteristics updated figure 46: i 2 c bus ac waveforms and measurement circuit updated figure 45: recommended nrst pin protection updated note 1 below table 49: i/o static characteristics updated table 20: peripheral current consumption updated table 14: maximum current consumption in run mode, code with data processing running from flash updated table 15: maximum current consumption in run mode, code with data processing running from ram updated table 16: maximum current consumption in sleep mode, code running from flash or ram updated table 17: typical and maximum current consumptions in stop and standby modes updated table 18: typical current consumption in run mode, code with data processing running from flash updated table 19: typical current consumption in sleep mode, code running from flash or ram updated table 24: lse oscillator characteristics (f lse = 32.768 khz) updated figure 22: asynchronous non-multiplexed sram/psram/nor read waveforms on page 62 added section 5.3.13: i/o current injection characteristics on page 83 18-jan-2012 3 section 2.3.26: gpios (general-purpose inputs/outputs) : modified text of last sentence. table 5: stm32f103xf and stm32f103xg pin definitions : updated pins pd0, pd1, osc_in, osc_out, pb8, pb9, and pf8. table 7: voltage characteristics : removed the previous footnotes 2 and 3 and added current footnote 2. table 8: current characteristics : updated footnotes 3 , 4 , and 5 . table 21: high-speed external user clock characteristics : replaced the t w(hse) min value by 5 (instead of 16). table 24: lse oscillator characteristics (f lse = 32.768 khz) : updated symbols and footnotes.
stm32f103xf, stm32f103xg revision history doc id 16554 rev 3 119/120 18-jan-2012 3 asynchronous waveforms and timings : added notes about t hclk clock period and fsmc_busturnaroundduration; updated conditions, modified table 31: asynchronous non-multiplexed sram/psram/nor read timings , table 32: asynchronous non-multiplexed sram/psram/nor write timings , table 34: asynchronous multiplexed psram/nor read timings , and table 35: asynchronous multiplexed psram/nor write timings ; added table 33: asynchronous read muxed . synchronous waveforms and timings : updated figure 27: synchronous multiplexed psram write timings ; updated table 36: synchronous multiplexed nor/psram read timings , table 37: synchronous multiplexed psram write timings , table 38: synchronous non- multiplexed nor/psram read timings , and table 39: synchronous non-multiplexed psram write timings . pc card/compactflash controller waveforms and timings : updated figure 35: pc card/compactflash controller waveforms for i/o space write access ; split switching characteristics into table 40: switching characteristics for pc card/cf read and write cycles in attribute/common space and table 41: switching characteristics for pc card/cf read and write cycles in i/o space , modified values, and removed footnote concerning preliminary values. nand controller waveforms and timings : updated conditions, split switching characteristics into table 42: switching characteristics for nand flash read cycles and table 43: switching characteristics for nand flash write cycles , and values modified. section 5.3.14: i/o port characteristics : updated footnote 1 of ta bl e 4 9 : i/o static characteristics ; updated output driving current . table 50: output voltage characteristics : swapped ?ttl and ?cmos? ports in the conditions column. table 54: i 2 c characteristics : updated footnote 2. updated table 58: sd / mmc characteristics . table 62: adc characteristics : updated footnote 1. table 64: adc accuracy - limited test conditions : updated footnote 3. table 67: ts characteristics : updated footnote 1. table 74. document revision history date revision changes
stm32f103xf, stm32f103xg 120/120 doc id 16554 rev 3 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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